The UART reference clock and core reset are controlled by the CRL register module.
When the controller registers are reset, it disables the controller, deasserts error and interrupt signals, clears the FIFO pointers, sets default configurations, and more. Refer to the reset value in the register reference document.
The base address
for the CRL register module is 0xFF5E_0000.
| Register Module and Name | Offset Address | Access Type | Description |
|---|---|---|---|
| Reference Clock | |||
|
CRL |
|
RW | Reference clock control from LPD clock controller |
| Controller Reset | |||
|
|
RW | Controller reset from LPD reset controller | |