Clock Frequency Divider Register Settings - Clock Frequency Divider Register Settings

Clock Frequency Divider Register Settings - Clock Frequency Divider Register Settings - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)

Document ID

AM011

Release Date

2026-03-06

Revision

1.9 English

The clock frequency divider receives the SDx_REF_CLK from the PMC clock controller to generate the DIV_CLK that is used for a 25 MHz or less SDx_CLK frequency. The SDx_REF_CLK reference clock frequency is controlled by the SD_EMMC CLK_CTRL [SDClkFreqDiv_L] and [SDClkFreqDiv_U] register bit fields. The register settings for each low-frequency setting is shown in the following table.

Table 1. SD/eMMC Clock Frequency Divider Register Settings
SDx_CLK Frequency (MHz)	SDx_REF_CLK Frequency)	CLK_CTRL Register	Divider Value (decimal)
SDx_CLK Frequency (MHz)	SDx_REF_CLK Frequency)	SDClkFreqDiv	Divider Value (decimal)
25.00	200 MHz	4	8
20.00		5	10
16.67		6	12
25.00	100 MHz	2	4
16.67		3	6
12.50		4	8
10.00		5	10
12.50	25 MHz	1	2
6.125		2	4
4.12		3	6
3.12		4	8
2.50		5	10