The Cache Coherent Interconnect for Accelerators (CCIX) block is coupled with two PCIe blocks, a DMA unit, and an L2 cache to create the CPM5. The CPM5 includes a 1 MB CPM L2-cache. For details, see the Versal Adaptive SoC CPM Mode for PCI Express Product Guide (PG346) and Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347).