The baud rate generator takes in the UARTx_REF_CLK clock and divides it down to 16x the desired baud rate for the I/O interface. The division is done using a 16-bit integer and a 6-bit fractional part.
The baud rate divider output should be set equal to the UARTx_REF_CLK / (16 × desired baud rate). The transmitter and receiver divide this output clock down by 16 to generate the final baud rate frequency.
The 16-bit integer is written into the BAUD_INTEGER [DIVINT] bit field. The 6-bit fractional part is written to the BAUD_FRACT [DIVFRAC] bit field.
The 6-bit fractional value is determined by:
The output clock (Baud16) of the baud rate divider is 16x the desired I/O baud rate. This signal is divided by 16 in the transmit and receive units for the I/O clock. A low number in the baud rate divisor gives a short bit period, and a high number in the baud rate divisor gives a long bit period.
Baud Rate Example
If the required baud rate is 230400 bps and the UARTx_REF_CLK is 4 MHz then:
- Baud_Rate_Divisor = (4^106) / (16 x 230400) = 1.085...
- [DIVINT] value = 1
- [DIVFRAC] value = integer of ((0.085 x 64) + 0.5) = integer of (5.94) = 5d = 000101b
The resulting baud rate divider = 1 + 5/64 = 1.078...
Baud Rate Range
The frequency selected for UART_REF_CLK must satisfy the required range of baud rates:
For example, for a range of baud rates from 110 to 460800 baud, the UARTx_REF_CLK frequency should be between 8 MHz and 110 MHz. To accommodate accuracy, add 10% margin.
UARTx_REF_CLK and LPD_LSBUS_CLK Dependency
The constraint requirement ensures that the UART has sufficient time to write the received data to the receive FIFO. This dependency only becomes important with very high baud rates and an unusually low LPD_LSBUS_CLK frequency.
For example, to provide a 921600 baud rate when UARTx_REF_CLK is 14.75 MHz, the LPD_LSBUS_CLK must be greater than or equal to 9 MHz; it is typically 100 MHz.
The frequency of UARTx_REF_CLK must be no more than 5/3 times faster than the frequency of LPD_LSBUS_CLK: