The following table lists the APU subsystem units.
| Unit | Description | Links |
|---|---|---|
| Compute Resources | ||
| APU processor engine | Two-core Arm® Cortex-A72, v8-architecture | See APU Processor Implementations for more processor-related functional units and Application Processing Unit for descriptions |
| APU_SWDT | System watchdog timer (SWDT) for software integrity monitoring | System Watchdog Timers |
| Interconnect | ||
| AXI interconnect | AXI interconnect switches, NIC-400 | Interconnect Switch Functionality |
| Cache coherent interconnect (CCI) | Connects APU processors and SMMU traffic to shared 1 MB L2 cache | Cache Coherent Interconnect |
| SMMU | System memory management unit with translation control unit and several individual translation buffer units (TBU) to translate virtual address into physical address | System Memory Management Unit |
| Non-coherent interconnect | I/O peripheral switch, and APB programming interface | – |
| APU_XMPU | Memory protection unit for register and system modules | Memory Protection Units |
| Test and Debug Resources | ||
| DBG registers | CoreSight | CoreSight Architecture |