16 TB NoC Interconnect Address Map - AM011

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2025-03-11
Revision
1.7 English

The 16 TB device-level address map includes groups of register modules and memory spaces accessible via the network on chip (NOC) interconnect.

Table 1. 16 TB NoC Interconnect Address Map
Destination Description Type Starting Address Size Firewall
DDRMC0_region0_mem DDR Memory Controller 0, Region 0 (lower 2GB) mem Std 0x0000_0000 2 GB DDRMC0_XMPU
LPD_AXI_PL_mmap PS to PL AXI Interface from LPD mmap Std 0x8000_0000 512 MB
FPD_AXI_PL_mmap PS to PL AXI Interface from FPD, lower mmap Std 0xA400_0000 192 MB
FPD_AXI_PL_mmap PS to PL AXI Interface from FPD, upper mmap Std 0xB000_0000 256 MB
OSPI_mem Octal-SPI Linear Mode memory space mem Std 0xC000_0000 512 MB LPD_XPPU (512MB)
CPM4_PCIe0_mem PCIe Region 0 in CPM4 mem CPM4 0xE000_0000 256 MB
PMC_Peripherals PMC Peripheral Register Modules mmap Std 0xF100_0000 112 MB
DBG_STM_mem Coresight Debug System Trace Macrocell mem 0xF800_0000 16 MB
GIC_Local_mmap RPU and APU local generic interrupt controller (GIC) access mmap Std 0xF900_0000 768 KB
FPD_Peripherals FPD Peripheral Register Modules reg Std 0xFD00_0000 16 MB
LPD_Peripherals_Memory LPD Memory and Peripheral Register Modules mmap Std 0xFE00_0000 ~11 MB LPD_XPPU (64KB, 1MB)
PSM_Peripherals_Memory PSM Memories and Register Modules mmap Std 0xFFC0_0000 1 MB LPD_XPPU (64KB a)
OCM_Memory On-chip Memory space mem Std 0xFFFC_0000 256 KB LPD_XPPU (64KB a)
RPU_TCM_Caches RPU TCM and Cache Memory Access Locations mem Std 0xFFE0_0000 864 KB LPD_XPPU (64KB a)
CPM5_Peripherals_Memory CPM5 Peripheral Register Modules and Memory mmap CPM5 0xE000_0000 ~464 MB
PMC0_alias Alias address to base PMC 0 (HN-D). (Alias engr names: PMC alias region x) Note: All four alias regions provide a window into associated local PMC address space 0xF000_0000 to 0xF7FF_FFFF (128 MB). mmap Std 0x001_0000_0000 128 MB
PMC1_alias Alias address to SSIT PMC 1 (HN-D) mmap SSIT 0x001_0800_0000 128 MB
PMC2_alias Alias address to SSIT PMC 2 (HN-D) mmap SSIT 0x001_1000_0000 128 MB
PMC3_alias Alias address to SSIT PMC 3 (HN-D) mmap SSIT 0x001_1800_0000 128 MB
FPD_AXI_PL_high PS FPD to PL AXI Interface, High Region (aka PS_TO_PL_0) mmap Std 0x004_0000_0000 8 GB
PCIe0_region1 PCIe Region 1 mmap 0x006_0000_0000 8 GB
DDRMC0_region1_mem DDR Memory Controller 0, Region 1 mem Std 0x008_0000_0000 32 GB
HBM0_mem High-bandwidth Memory Controller 0 (HN-F port) mem HBM 0x040_0000_0000 64 GB
HBM1_mem High-bandwidth Memory Controller 1 (HN-F port) mem HBM 0x050_0000_0000 64 GB
HBM2_mem High-bandwidth Memory Controller 2 (HN-F port) mem HBM 0x060_0000_0000 64 GB
HBM3_mem High-bandwidth Memory Controller 3 (HN-F port) mem HBM 0x070_0000_0000 64 GB
PCIe_region_2 PCIe Region 2 mmap CPM 0x080_0000_0000 256 GB
DDRMC0_region_2_mem DDR Memory Controller 0, Region 2 mem Std 0x0C0_0000_0000 256 GB
DDRMC0_region_3_mem DDR Memory Controller 0, Region 3 mem Std 0x100_0000_0000 734 GB
AI_Engine AI Engine Programming and Interface Tiles mmap AIE 0x200_0000_0000 4 GB
PL_LO_mmap PL Memory Space, Low Region mmap Std 0x201_0000_0000 ~4 TB
PS_PL_mmap PS to PL Memory Space mmap Std 0x400_0000_0000 1 TB
DDRMC1_region0_mem DDR memory controller 1, region 0 mem DDRMC 0x500_0000_0000 512 GB DDRMC1_XMPU
DDRMC1_region1_mem DDR memory controller 1, region 1 mem DDRMC 0x580_0000_0000 512 GB DDRMC1_XMPU
DDRMC2_region0_mem DDR memory controller 2, region 0 mem DDRMC 0x600_0000_0000 512 GB DDRMC2_XMPU
DDRMC2_region1_mem DDR memory controller 2, region 1 mem DDRMC 0x680_0000_0000 512 GB DDRMC2_XMPU
DDRMC3_region0_mem DDR memory controller 3, region 0 mem DDRMC 0x700_0000_0000 512 GB DDRMC3_XMPU
DDRMC3_region1_mem DDR memory controller 3, region 1 mem DDRMC 0x780_0000_0000 512 GB DDRMC3_XMPU
PL_HI_mmap PL Memory Space, High Region mmap Std 0x800_0000_0000 8 TB