X5PHIO_XCVR_X2 - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2025-03-07
Revision
1.6 English

The following table shows the X5PHIO_XCVR_X2 Ports.

Table 1. X5PHIO_XCVR_X2 Ports
Port Name Width Input/Output Clock Domain Description
CFGXCV_SCAN_DATA_OUT_INT [4:0] Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CFGXCV_SCAN_EN   Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CFGXCV_SCAN_MODE   Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CFGXCV_SCAN_MODE_RST   Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CFGXCV_SCAN_RST_BYP   Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CMU2XCV_DCI [16:0] Input   Reserved. Used by simulation and Advanced I/O Wizard only.
CTRLXCV_SCAN_DATA_IN_INT [5:0] Input    
DCI_BUS_BUF_OUT [16:0] Output    
DIFF_N   inout   Connects to the pin (n-side when using differential standards).
DIFF_P   inout   Connects to the pin (p-side when using differential standards).
DQS_DLY_OUT_R   Output   For BIT[2], capture clock output after the delay line. To be used for forwarding the capture clock to multiple Octads.
DQS_IN_R   Input   Connects to CMPHY_OCTAD. Clock gating and rank switching control.
PHY2XCV_RD_CTL [7:0] Input   Connects to XCVR_X2_0. DQS gating and rank switching control to xcvr_x2(0).
PHY2XCV_WR_CTL [7:0] Input   TX clock gate control <7:6> : wldly_update, bit_active <5:4> : rank <1:0> : slot
PHY2XCV_WR_DQ [31:0] Input   [31:16] tristate serializer data

[7:0] serializer data
PHY2XCV_2TO1_CLK   Input   Clock input for Low Latency 2to1 mode.
PLL_CLK0   Input   High-speed clock. Connects to X5PLL CLKOUTPHY_0 port.
PLL_CLK90   Input   High-speed clock. Connects to X5PLL CLKOUTPHY_90 port.
RIU2XCV_CA   Input   Serial RIU interface. Connects to CMPHY_OCTAD. Serial command and address pin.
RIU2XCV_CK   Input   Serial RIU interface. Connects to CMPHY_OCTAD. Serial clock pin.
RIU2XCV_RST   Input   Serial RIU interface. Connects to CMPHY_OCTAD. Asynchronous reset (confirm if sync deassert).
RIU2XCV_WR   Input   Serial RIU interface. Connects to CMPHY_OCTAD. Serial write data pin.
XCV2CGL_RX0_RDQS_P_OUT_CLK   Output   Reserved
XCV2CGL_RX1_RDQS_P_OUT_CLK   Output   Reserved
XCV2CGL_RX1_NDQS_DLY_IN   Input   Reserved
XCV2CGL_RX2_NDQS_DLY_IN   Input   Reserved
XCV2CLK_DIV64_CLK   Output    
XCV2CLK_RIU_CLK0_DCD_ADJ [3:0] Output   Duty cycle correction code for CLK0.
XCV2CLK_RIU_CLK0_DCD_ADJ_SEL   Output   Duty cycle correction select control for CLK0.
XCV2CLK_RIU_CLK90_DCD_ADJ [3:0] Output   Duty cycle correction code for CLK90.
XCV2CLK_RIU_CLK90_DCD_ADJ_SEL   Output   Duty cycle correction select control for CLK90.
XCV2PHY_RD_CLK [1:0] Output   Two clocks per xcvr_x2 that is a divide by four of NDQS per DQ bit.
XCV2PHY_RD_DQ [15:0] Output   [15: 8] = read data from xcvr_x2(0) bit 1.

[7:0] = read data from xcvr_x2(0) bit 0.
XCV2PHY_WR_CLK   Output   Clock for write data and read/write control (clock and DQS gating). Clock rate DDR/8. To xcvr_x2(1)
XCV2PHYPLL_RX_OUT_M   Output    
XCV2PHYPLL_RX_OUT_S   Output    
XCV2RIU_CK   Output   Serial RIU clock (maximum 600 MHz) for read data.
XCV2RIU_RD [3:0] Output   Serial RIU read data.
XCV2XCV_CPHY_CLK_IN   Input   Reserved for CPHY clock recovery.
XCV2XCV_CPHY_CLK_OUT   Output   Reserved for CPHY clock recovery.
XCV2XCV_NDQS_DLY_O   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Delayed negative edge-aligned capture clock output used for DQS used for data centering.
XCV2XCV_NDQS_IN   Input   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used. Capture clock input for falling edge data. NDQS clock input.
XCV2XCV_NDQS_O   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Negative edge aligned capture clock output used for DQS used for clock centering.
XCV2XCV_PAD_N   Input   Reserved for future use.
XCV2XCV_PAD_P   Input  

Reserved for future use.
XCV2XCV_PDQS_DLY_O   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Delayed positive edge-aligned capture clock output used for DQS used for data centering.
XCV2XCV_PDQS_IN   Input   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on if clock centering or data centering is being used. Capture clock input for rising edge data. PDQS clock input.
XCV2XCV_PDQS_O   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Positive edge-aligned capture clock output used for DQS used for clock centering.
XCV2XCV_RX0_RDQS_IN   Input   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used.
XCV2XCV_RX0_RDQS_OUT   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used.
XCV2XCV_RX1_RDQS_IN   Input   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used.
XCV2XCV_RX1_RDQS_OUT   Output   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used.
XCV2XCV_RX2_RDQS_IN   Input   X5IO PHY clocking. Setup by X5IO Wizard based on x4/x8/x30 clocking requirements for the capture clock. Connectivity additionally dependent based on whether clock centering or data centering is being used.
XCV2XCV_RX2TX_DIN [1:0] Input   Dedicated output for XCC pin used when pin is to be used as the negative edge capture clock source. Delayed captured clock must be used when routing to entire bank.
XCV2XCV_RX2TX_DOUT [1:0] Output   Dedicated input to be connected to source clock used for the negative-edge capture clock source.
XCV2XCV_VREF_H1M_I   Input   Dedicated output for XCC pin used when pin is to be used as the negative-edge capture clock source.
XCV2XCV_VREF_H1M_O   Output   Reserved. Advanced I/O Wizard use only.
XCV2XCV_VREF_H1P_I   Input   Reserved. Advanced I.O Wizard use only.
XCV2XCV_VREF_H1P_O   Output   Dedicated output for XCC pin used when pin is to be used as the positive edge capture clock source. Delayed captured clock must be used when routing to entire bank.

The following table shows the X5PHIO_XCVR_X2 attributes.

Table 2. X5PHIO XCVR_X2 Attributes
Attribute Type Values Default Description
ADL_H1ME_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1ME_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1ME_OFST_VALUE_M BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1ME_OFST_VALUE_S BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1MO_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1MO_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1MO_OFST_VALUE_M BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1MO_OFST_VALUE_S BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1PE_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1PE_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1PE_OFST_VALUE_M BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1PE_OFST_VALUE_S BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1PO_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1PO_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Reserved
ADL_H1PO_OFST_VALUE_M BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
ADL_H1PO_OFST_VALUE_S BINARY 4'b0000 to 4'b1111 4'b0000 Reserved
APBCLK_FREQ DECIMAL 0 to 500 0 Frequency of APB Clock.
CCIO_EN_M STRING FALSE, TRUE FALSE Enables dedicated clock routing for DIFF_P.
CCIO_EN_S STRING FALSE, TRUE FALSE Enables dedicated clock routing for DIFF_N.
CPHY_TERM_M STRING FALSE, TRUE FALSE When TRUE enables CPHY RX termination, DIFF_P.
CPHY_TERM_S STRING FALSE, TRUE FALSE When TRUE enables CPHY RX termination, DIFF_N.
CTLE_EQ_M STRING CTLE_EQ_NONE, CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8 CTLE_EQ_NONE Continuous Time Linear Equalization (CTLE). DIFF_P
CTLE_EQ_S STRING CTLE_EQ_NONE, CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8 CTLE_EQ_NONE Continuous Time Linear Equalization (CTLE). DIFF_N
CTLE_H1M_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 CTLE H1M offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset, DIFF_P
CTLE_H1M_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 CTLE H1M offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
DIFF_N
CTLE_H1M_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 CTLE H1M offset cancellation code. DIFF_P
CTLE_H1M_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 CTLE H1M offset cancellation code. DIFF_N
CTLE_H1P_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 CTLE H1P offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
DIFF_P
CTLE_H1P_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 CTLE H1P offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
DIFF_N
CTLE_H1P_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 CTLE H1P offset cancellation code. DIFF_P
CTLE_H1P_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 CTLE H1P offset cancellation code. DIFF_N
DFE_EQ_M String DFE_NONE, DFE_1TAP_MANUAL, DFE_1TAP_AUTO, DFE_2TAP_MANUAL, DFE_2TAP_AUTO DFE_NONE Decision feedback equalization (DFE), DIFF_P.
DFE_EQ_S String DFE_NONE, DFE_1TAP_MANUAL, DFE_1TAP_AUTO, DFE_2TAP_MANUAL, DFE_2TAP_AUTO DFE_NONE DFE, DIFF_N.
DFE_H2_NEG_POL_M BINARY 1'b0, 1'b1 1'b0 DFE second tap polarity.
  • 1: To cancel negative weight post cursor
  • 0: To cancel positive weight post cursor
DIFF_P
DFE_H2_NEG_POL_S BINARY 1'b0, 1'b1 1'b0 DFE second tap polarity.
  • 1: To cancel negative weight post cursor
  • 0: To cancel positive weight post cursor
DIFF_N
DFE_H2_TAP_WEIGHT_M BINARY 5'b00000 to 5'b11111 5'b00000 DFE second tap weight code. DIFF_P
DFE_H2_TAP_WEIGHT_S BINARY 5'b00000 to 5'b11111 5'b00000 DFE second tap weight code. DIFF_N
DIFF_TERM STRING FALSE, TRUE FALSE Turns the built-in differential termination on (TRUE) or off (FALSE).
DQS_ANA_DETECTION_M STRING FALSE, TRUE FALSE Reserved
DQS_ANA_DETECTION_S STRING FALSE, TRUE FALSE Reserved
DQS_BIAS_M STRING FALSE, TRUE FALSE Provides pull-up/pull-down feature required for some DQS memory interface pins or provides DC bias for certain LVDS applications. DIFF_P
DRIVE_M DECIMAL 2, 4, 6, 8 8 Specifies the drive strength [mA] of the output when using LVCMOS standards. DIFF_P
DRIVE_S DECIMAL 2, 4, 6, 8 8 Specifies the drive strength [mA] of the output when using LVCMOS standards. DIFF_N
EN_OMUX STRING FALSE, TRUE FALSE  
ISTANDARD_M STRING

Single Ended

POD10, POD11, POD12, HSTL_I_12, HSUL_12, LVCMOS10, LVCMOS11, LVCMOS12, LVSTL_11, LVSTL05_10, LVSTL06_12, SSTL10, SSTL11, SSTL12

Differential

DIFF_HSTL_I_12, DIFF_HSUL_12, DIFF_LVSTL_11, DIFF_LVSTL05_10, DIFF_LVSTL06_12, DIFF_POD10, DIFF_POD11, DIFF_POD12, DIFF_SSTL10, DIFF_SSTL11, DIFF_SSTL12, LVDS12

UNUSED Assigns an input I/O standard to DIFF_P.
ISTANDARD_S STRING UNUSED Assigns an input I/O standard to DIFF_N.
LL_2TO1_MODE_0 STRING FALSE, TRUE FALSE When set to TRUE, DIFF_P uses the low latency 2 to 1 output on DIFF_P.
LL_2TO1_MODE_1 STRING FALSE, TRUE FALSE When set to TRUE, DIFF_P uses the low latency 2 to 1 output on DIFF_N.
OSTANDARD_M STRING

Single Ended

POD10, POD11, POD12, HSTL_I_12, HSUL_12, LVCMOS10, LVCMOS11, LVCMOS12, LVSTL_11, LVSTL05_10, LVSTL06_12, SSTL10, SSTL11, SSTL12

Differential

DIFF_HSTL_I_12, DIFF_HSUL_12, DIFF_LVSTL_11, DIFF_LVSTL05_10, DIFF_LVSTL06_12, DIFF_POD10, DIFF_POD11, DIFF_POD12, DIFF_SSTL10, DIFF_SSTL11, DIFF_SSTL12, LVDS12

UNUSED Assigns an output I/O standard to DIFF_P.
OSTANDARD_S STRING UNUSED Assigns an output I/O standard to DIFF_N.
PHY2XCV_LATENCY DECIMAL 8, 2, 4, 6 8  
RD_CTL_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000  
RIUCLK_DBLR_BYPASS STRING FALSE, TRUE FALSE  
ROUTETHRU_0 STRING TRUE, FALSE TRUE When set to TRUE, X5IO PHY logic is bypassed for DIFF_P.
ROUTETHRU_1 STRING TRUE, FALSE TRUE When set to TRUE, X5IO PHY logic is bypassed for DIFF_N.
RX_DATA_WIDTH_M DECIMAL 8, 2, 4, 16 8 Deserialization data width (1:2, 1:4, 1:8, or 1:16) for X5IO PHY receiver for DIFF_P.
RX_DATA_WIDTH_S DECIMAL 8, 2, 4, 16 8 Deserialization data width (1:2, 1:4, 1:8, or 1:16) for X5IO PHY receiver for DIFF_N.
RX2TX_LOOPBACK_M STRING TRUE, FALSE FALSE Loopback for DIFF_P
RX2TX_LOOPBACK_S STRING TRUE, FALSE FALSE Loopback for DIFF_N
SA_H1ME_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Sampler H1ME offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset.
DIFF_P
SA_H1ME_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Sampler H1ME offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset.
DIFF_N
SA_H1ME_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1ME offset cancellation code. DIFF_P
SA_H1ME_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1ME offset cancellation code. DIFF_N
SA_H1MO_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Sampler H1MO offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1MO_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Sampler H1MO offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1MO_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1MO offset cancellation code
SA_H1MO_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1MO offset cancellation code
SA_H1PE_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Sampler H1PE offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1PE_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Sampler H1PE offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1PE_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1PE offset cancellation code
SA_H1PE_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1PE offset cancellation code
SA_H1PO_OFST_POL_M BINARY 1'b0, 1'b1 1'b0 Sampler H1PO offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1PO_OFST_POL_S BINARY 1'b0, 1'b1 1'b0 Sampler H1PO offset cancellation polarity.
  • 1: To cancel negative offset
  • 0: To cancel positive offset
SA_H1PO_OFST_VAL_M BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1PO offset cancellation code
SA_H1PO_OFST_VAL_S BINARY 6'b000000 to 6'b111111 6'b000000 Sampler H1PO offset cancellation code
TX2RX_PREDRV_LOOPBACK_M STRING TRUE, FALSE FALSE Loopback for DIFF_P
TX2RX_PREDRV_LOOPBACK_M STRING TRUE, FALSE FALSE Loopback for DIFF_N
TX_DATA_WIDTH DECIMAL 8, 2, 4, 16 8 Serialization data width for X5IO PHY transmitter. 1:2, 1:4, 1:8, or 1:16
TX_INIT_T STRING FALSE, TRUE FALSE
  • 1'b0: Sets the tristate control signal during configuration and reset.
  • 1'b1: Sets the tristate control signal during configuration and reset.
TX_INIT_0 STRING FALSE, TRUE FALSE
  • 1'b0: Sets the TX DIFF_P value associated with BIT[x] during configuration and reset.
  • 1'b1: Sets the TX DIFF_P value associated with BIT[x] during configuration and reset.
TX_INIT_1 STRING FALSE, TRUE FALSE When TRUE, sets all flops on tx1 dq serializer to all 0, when reset.
VREF_H1M_VALUE_M BINARY 10'b0000000000 to 10'b1111111111 10'b1000000000 VREF_H1M value code.
VREF_H1M_VALUE_S BINARY 10'b0000000000 to 10'b1111111111 10'b1000000000 VREF_H1M value code.
VREF_H1P_PER_OCTAD_M BINARY 1'b1, 1'b0 1'b1
  • 1: Select common VREF_H1P. If this is enabled, the VREF_H1P in Pin<5> needs to be enabled. The VREF_H1P from pin<5> has the access to all RXs in the same Octad.
  • 0: Select per I/O VREF_H1P.
VREF_H1P_PER_OCTAD_S BINARY 1'b1, 1'b0 1'b1
  • 1: Select common VREF_H1P. If this is enabled, the VREF_H1P in Pin<5> needs to be enabled. The VREF_H1P from pin<5> has the access to all RXs in the same Octad.
  • 0: Select per I/O VREF_H1P.
VREF_H1P_VALUE_M BINARY 10'b0000000000 to 10'b1111111111 10'b1000000000 VREF_H1P value code.
VREF_H1P_VALUE_S BINARY 10'b0000000000 to 10'b1111111111 10'b1000000000 VREF_H1P value code.
WR_CTL_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved for Advanced I/O Wizard.
WR_DQ0_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved for Advanced I/O Wizard.
WR_DQ1_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved for Advanced I/O Wizard.
WR_EN0_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved for Advanced I/O Wizard.
WR_EN1_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved for Advanced I/O Wizard.