X5PHIO_CMU_X32 - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2025-03-07
Revision
1.6 English

The following table shows the X5PHIO_CMU_X32 ports.

Table 1. X5PHIO_CMU_X32 Ports
Port Name Width Input/Output Clock Domain Description
APB2CMU_CA Input Serial RIU interface. Connects to CMPHY_OCTAD. Serial command and address pin.
APB2CMU_CK Input Serial RIU interface. Connects to CMPHY_OCTAD. Serial clock pin.
APB2CMU_RST Input Serial RIU interface. Connects to CMPHY_OCTAD. Asynchronous reset. (Confirm if sync deassert.)
APB2CMU_WR Input Serial RIU interface. Connects to CMPHY_OCTAD. Serial write data pin.
CMU_SCAN_EN Input DFX scan enable
CMU_SCAN_MODE Input DFX scan mode
CMU_SCAN_MODE_RST_B Input DFX Scan mode reset. Active low
CMU_SCAN_RST_BYP Input DFX scan reset bypass
CMU2APB_CK Output CMU to APB clock.
CMU2APB_RD [3:0] Output CMU to APB read data.
CMU2CMU_RCAL_IN [14:0] Input Calibration. Reserved for X5IO wizard.
CMU2CMU_RCAL_OUT [14:0] Output Calibration. Reserved for X5IO wizard.
CMU2XCV_DCI [16:0] Output Calibration. Reserved for X5IO wizard.
DCI_LOCK_DONE_DWN Output Calibration. Reserved for X5IO wizard.
DCI_LOCK_DONE_UP Output Calibration. Reserved for X5IO wizard.
DCI_LOCK_INIT_DWN Input Calibration. Reserved for X5IO wizard.
DCI_LOCK_INIT_UP Input Calibration. Reserved for X5IO wizard.
MASTER_EN_PIN Input Calibration. Reserved for X5IO wizard.
OCTAD_VREF_H1M Input Calibration. Reserved for X5IO wizard.
OCTAD_VREF_H1P Input Calibration. Reserved for X5IO wizard.