X5PHIO_CMUIF - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID: AM010
Release Date: 2025-05-22
Revision: 1.7 English

The following table shows the X5PHIO_CMUIF ports.

Table 1. X5PHIO_CMUIF Ports
Port Name	Width	Input/Output	Clock Domain	Description
APB2CMU_CA		Output		Serial RIU interface. Connects to CMPHY_OCTAD. Serial command and address pin.
APB2CMU_CK		Output		Serial RIU interface. Connects to CMPHY_OCTAD. Serial clock pin.
APB2CMU_RST		Output		Serial RIU interface. Connects to CMPHY_OCTAD. Asynchronous reset. (Confirm if sync deassert.)
APB2CMU_WR		Output		Serial RIU interface. Connects to CMPHY_OCTAD. Serial write data pin.
CMU2APB_CK		Input		APB clock.
CMU2APB_RD	[3:0]	Input		APB read data.
PADDR	[9:0]	Input		APB address.
PCLK		Input		APB clock
PENABLE		Input		APB enable. This signal indicates the second and subsequent cycles of an APB transfer.
PRDATA	[15:0]	Output		APB read data. The selected slave drives this bus during read cycles when m_apb_pwrite is Low.
PREADY		Output		APB ready. The APB slave uses this signal to extend an APB transfer. The port width depends on the number of slave interfaces created.
PRESETN		Input		APB preset (active-Low).
PSEL		Input		APB select
PSLVERR		Output		APB slave error. This signal indicates a transfer failure.
PWDATA	[15:0]	Input		APB write data.
PWRITE		Input		APB direction. This signal indicates an APB write access when High and an APB read access when Low.

The following table shows the X5PHIO_CMUIF attributes.

Table 2. X5PHIO_CMUIF Attributes
Attribute	Type	Values	Default	Description
APBCLK_FREQ	DECIMAL	0 to 500	100	APB frequency
DMC_APB_SEL_CMU	STRING	FALSE, TRUE	FALSE	Enables DMC interface