X5IO PHY Octad - AM010

Each X5IO bank is made up of four Octads or 32 bits. There are two shared X5PLLs that can connect to any of the eight XCVR_OCTADs for every two banks, such as 704 and 705. X5PLLs additionally support limited cascaded routing for X5IOs in neighboring banks as supported by the Vivado tools.

Figure 1. X5IO Bank - 32 Bits

The fabric interface to the X5IO PHY is handled by the CMPHY_OCTAD. The CMPHY_OCTAD provides a common interface for designs to connect the PL to the X5IO PHY. Independent transmit and receive FIFOs allow each X5IO PHY to support up to 16-bit serialization and 16-bit deserialization.

The CMPHY_OCTAD connects to four X5PHIO_XCVR_X2. Each X5PHIO_XCVR_X2 can support a differential pin pair or two single-ended pins. A single X5PHIO_XCVR_X2 can drive bit 0 and 1 as a differential pin pair or control bit 0 and 1 as two single-ended pins. Pins not used for X5IO PHY are still available.

The following figure shows the transmit and receive datapaths for the X5IO PHY bitslice.

Figure 2. X5IO PHY Bit