The X5IO PHY is the high-performance I/O interface in the X5IO banks. The X5IO PHY are organized in banks of 32 I/Os. The I/Os are grouped together as 8-bit Octads or four 2-bit transceivers (XCVR_X2) for each Octad.
The X5IO PHY is controlled by four main primitives. The X5IO PHY contains the CMPHY_OCTAD, which contains the fabric interface and handles the communication with the rest of the X5IO primitives. The X5PHIO_XCVR_X2 supports the serialization and deserialization and I/O controls. Each X5PHIO_XCVR_X2 supports one differential pin pair or two single-ended pins. The X5PHIO_CMU provides the biasing and calibrated impedance codes for the I/Os. The X5PLL is the PLL used for the X5IO PHY (see the following table).
| Bank Type | X5IO | XPHY |
|---|---|---|
| Pins Supported | Eight bits in an Octad (CMPHY_OCTAD) |
Six nibbleslices in a nibble (XPHY) |
| Data Width | 2/4/8/16 | 2/4/8 |
| Clock Source | X5PLL X5PLL_S2P X5PHIO_DCCINVBUF X5PLL_INTF |
XPLL |
| Receiver Capture Clock Placement (Strobe or Clock pin) |
Bit2
(See Table 2 for valid X5IO capture clock pin sites) |
Nibbleslice0 |
| RX FIFO | Yes (CMPHY_OCTAD) |
Yes (XPHY) |
| TX FIFO | Yes (CMPHY_OCTAD) |
No |
The X5IO PHY banks support a number of enhancements to allow higher performance. X5IO PHY is used to support the following applications:
- DDR5 (5.6 Gb/s)
- LPDDR5 (6.4 Gb/s)
- DDR4 (3.2 Gb/s)
- LPDDR4 (4.3 Gb/s)
- 1000Base-X and SGMII
- ONFI and Toggle NAND Flash