X5IO IOB Supported Single-Ended Standards Attributes and Description - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2025-03-07
Revision
1.6 English

LVCMOS

The low_voltages CMOS standards are a widely used standard. The LVCMOS standards in X5IO banks have definable drive and slew control. LVCMOS12 (1.2V), LVCMOS11 (1.1V), and LVCMOS10 (1.0V) are supported in the X5IO IOB.

Table 1. Allowed Attributes for LVCMOS Primitives
Attributes Input Buffer Output and Bidirectional Buffer
Allowed Values Allowed Values
IOSTANDARD LVCMOS12, LVCMOS11, LVCMOS10 LVCMOS12, LVCMOS11, LVCMOS10
DRIVE N/A 2, 4, 6, 8 (Default)
SLEW N/A FAST (Default), MEDIUM, SLOW

LVSTL

The low-voltage swing terminated logic (LVSTL_11, LVSTL05_10, and LVSTL06_12) standards are optimized for lower-power memory interfaces. LVSTL06_12 is compatible with LVSTL06 interfaces but is powered at 1.2V while LVSTL05_10 is compatible with LVSTL05 but is powered at 1.0V. LVSTL standards are commonly used for LPDDR4 and LPDDR5 applications. LVSTL standards have receive side termination to ground.

Table 2. Allowed Attributes for LVSTL Primitives
Attributes Input Buffer Bidirectional Buffers Output Buffer
Allowed Values Allowed Values Allowed Values
IOSTANDARD LVSTL_11, LVSTL05_10, LVSTL06_12 LVSTL_11, LVSTL05_10, LVSTL06_12 LVSTL_11, LVSTL05_10, LVSTL06_12
SLEW N/A FAST (Default), MEDIUM, SLOW FAST (Default), MEDIUM, SLOW
ODT RTT_40 (Default), RTT_48, RTT_60, RTT_NONE RTT_40 (Default), RTT_48, RTT_60, RTT_NONE N/A
OUTPUT_IMPEDANCE   RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE (Default)
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_NONE (Default) CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_NONE (Default) N/A
DC_BIAS DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 N/A
PRE_EMPHASIS ( LVSTL_11 and LVSTL06_12 ONLY) N/A RDRV_NONE(Default), RDRV_240 RDRV_NONE(Default), RDRV_240

HSTL and SSTL

Typically used for high-speed buses, the HSTL and SSTL standards leverage VREF based receiver with split-end termination. HSTL_I_12 (1.2V), SSTL12 (1.2V), SSTL11 (1.1V), and SSTL10 (1.0V) all provide high performance interfaces commonly used in high-speed memory interface applications.

Table 3. Allowed Attributes for HSTL and SSTL Primitives
Attributes Input Buffer Bidirectional Buffer Output Buffer
Allowed Values Allowed Values Allowed Values
IOSTANDARD HSTL_I_12, SSTL12, SSTL11 and SSTL10 HSTL_I_12, SSTL12, SSTL11 and SSTL10 HSTL_I_12, SSTL12, SSTL11 and SSTL10
SLEW N/A FAST (Default), MEDIUM, SLOW FAST (Default), MEDIUM, SLOW
ODT RTT_40 (Default), RTT_48, RTT_60, RTT_NONE RTT_40 (Default), RTT_48, RTT_60, RTT_NONE N/A
OUTPUT_IMPEDANCE N/A RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE
DC_BIAS DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 NA

POD

Pseudo open drain (POD) standards POD12 (1.2V), POD11 (1.1V) and POD10 (1.0V) are commonly used for DDR4 and DDR5 applications. They leverage end termination to VCCO.

Table 4. Allowed Attributes for POD Primitives
Attributes Input Buffer Bidirectional Buffer Output Buffer
Allowed Values Allowed Values Allowed Values
IOSTANDARD POD12, POD11, POD10 POD12, POD11, POD10 POD12, POD11, POD10
SLEW N/A FAST (Default), MEDIUM, SLOW FAST, MEDIUM, SLOW
ODT RTT_40 (Default), RTT_48, RTT_60, RTT_NONE RTT_40 (Default), RTT_48, RTT_60, RTT_NONE N/A
OUTPUT_IMPEDANCE N/A RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60, RDRV_NONE_NONE
DC_BIAS DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0 , DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 N/A
CTLE_EQ (POD12 and POD11 only) CTLE_EQ_NONE (Default); CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8 CTLE_EQ_NONE (Default); CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8 N/A
DFE_EQ DFE_NONE (Default), DFE_1TAP_MANUAL (DDR5 interfaces only), DFE_1TAP_AUTO (DDR5 interfaces only) DFE_NONE (Default), DFE_1TAP_MANUAL (DDR5 interfaces only), DFE_1TAP_AUTO (DDR5 interfaces only)  
PRE_EMPHASIS N/A RDRV_NONE(Default), RDRV_240 RDRV_NONE(Default), RDRV_240

HSUL

The high-speed unterminated logic (HSUL_12) standard is for LPDDR2 and LPDDR3 memory buses. HSUL_12 is defined by the JEDEC standard JESD8-22. X5IO banks support this standard for single-ended signaling and differential signaling. Similar to SSTL, this standard also requires a differential amplifier input buffer and a push-pull output buffer. HSUL_12 buffers leverage end termination to VCCO.

Table 5. Allowed Attributes for HSUL Primitives
Attributes Input Buffer Bidirectional Buffer Output Buffer
Allowed Values Allowed Values Allowed Values
IOSTANDARD HSUL_12 HSUL_12 HSUL_12
DRIVE N/A 2, 4, 6, 8 (Default) 2, 4, 6, 8 (Default)
SLEW N/A FAST (Default), MEDIUM, SLOW FAST (Default), MEDIUM, SLOW
RTT_40 , RTT_48, RTT_60, RTT_NONE (Default) RTT_120 (Default), RTT_240, RTT_NONE RTT_120 (Default), RTT_240, RTT_NONE  
DC_BIAS DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0 , DC_BIAS_1, DC_BIAS_2, DC_BIAS_3