X5IO IOB Supported Differential Standards and Attributes - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2025-03-07
Revision
1.6 English

DIFF_SSTL and DIFF_HSTL

The stub-series terminated logic (SSTL) for 1.2V (DIFF_SSTL12), 1.1V (DIFF_SSTL11), and 1.0V (DIFF_SSTL10) are differential I/O standards used for general-purpose memory buses.

Table 1. Allowed Attributes for DIFF_SSTL12, DIFF_SSTL11, DIFF_SSTL10 I/O, and DIFF_HSTL_I_12 Primitives
Attributes IBUFDS/IBUFDSE3 IOBUF/IOBUFE3 OBUFDS/OBUFTDS
Allowed Values Allowed Values Allowed Value
IOSTANDARD DIFF_SSTL12, DIFF_SSTL11, DIFF_SSTL10,DIFF_HSTL_I_12 DIFF_SSTL12, DIFF_SSTL11, DIFF_SSTL10,DIFF_HSTL_I_12 DIFF_SSTL12, DIFF_SSTL11, DIFF_SSTL10,DIFF_HSTL_I_12
SLEW N/A FAST, MEDIUM, SLOW (Default) FAST, MEDIUM, SLOW (Default)
OUTPUT_IMPEDANCE N/A RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60 RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60
ODT RTT_40 (Default), RTT_48, RTT_60, RTT_NONE RTT_40 (Default), RTT_48, RTT_60, RTT_NONE N/A
DQS_BIAS (DIFF_SSTL12 ONLY) DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3 DC_BIAS_0, DC_BIAS_1, DC_BIAS_2, DC_BIAS_3
DC_BIAS (DIFF_SSTL12, DIFF_SSTL11, DIFF_SSTL10 ONLY) TRUE TRUE TRUE

DIFF_HSUL12

The high-speed unterminated logic (HSUL) DIFF_HSUL12 differential standard is optimized for low-power memory interfaces.

Table 2. Allowed Attributes for DIFF_HSUL_12 and I/O Primitives
Attributes IBUFDS/IBUFDSE3 IOBUF/IOBUFE3 OBUFDS/OBUFTDS
IOSTANDARD DIFF_HSUL_12 DIFF_HSUL_12 DIFF_HSUL_12
OUTPUT_IMPEDANCE N/A RDRV_40_40(Default), RDRV_48_48, RDRV_60_60 RDRV_40_40(Default), RDRV_48_48, RDRV_60_60
ODT RTT_120 (Default), RTT_240, RTT_NONE RTT_120 (Default), RTT_240, RTT_NONE N/A

DIFF_LVSTL

The low-voltage swing terminated logic (DIFF_LVSTL_11, DIFF_LVSTL06_12, and DIFF_LVSTL05_10) standards are optimized for low-power memory interfaces. DIFF_LVSTL06_12 is compatible with differential LVSTL06 interfaces but is powered at 1.2V while DIFF_LVSTL05_10 is compatible with LVSTL05 but is powered at 1.0V.

Table 3. Allowed Attributes for DIFF_LVSTL Primitives
Attributes IBUFDS/IBUFDSE3 IOBUFDS/IOBUFDSE3 OBUFDS/OBUFTDS
IOSTANDARD DIFF_LVSTL_11, DIFF_LVSTL06_12, DIFF_LVSTL05_10 DIFF_LVSTL_11, DIFF_LVSTL06_12, DIFF_LVSTL05_10 DIFF_LVSTL_11, DIFF_LVSTL06_12, DIFF_LVSTL05_10
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default) CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default) N/A
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3
OUTPUT_IMPEDANCE N/A RTT_40 (Default), RTT_48, RTT_60 RTT_40 (Default), RTT_48, RTT_60
SLEW   FAST (Default), MEDUIM, SLOW FAST (Default), MEDUIM, SLOW
ODT RTT_40_40 (Default), RTT_48_48, RTT_60_60, RTT_NONE RTT_40_40 (Default), RTT_48_48, RTT_60_60, RTT_NONE  

LVDS

LVDS12 is a 1.2V powered standard designed to interface with the low-voltage differential signaling (LVDS) standard. It is compatible with EIA/TIA electrical specifications but is powered at 1.2V to operate within the X5IO bank architecture.

Important: In X5IO, LVDS12 is powered at 1.2V. Because it has a common mode lower than many LVDS components, care must be taken to ensure the downstream devices are electrically compatible. AC coupling should be considered to achieve compatibility with the X5IO's LVDS interface.
Table 4. Allowed Attributes for LVDS12 and I/O Primitives
Attributes IBUFDS/IBUFDSE3 IOBUFDS/IOBUFDSE3 OBUFDS/OBUFTDS
IOSTANDARD LVDS12 LVDS12 LVDS12
DIFF_TERM_ADV TERM_100, TERM_NONE (Default) TERM_100, TERM_NONE (Default) N/A
LVDS_PRE_EMPHASIS N/A FALSE (Default), TRUE FALSE (Default), TRUE
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default) CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default) N/A
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3
  1. The bidirectional configuration on these I/O standards is a fixed impedance structure optimized to 100Ω differential. They are only intended to be used in point-to-point transmissions that do not have turn around timing requirements.

DIFF_POD

The differential (DIFF_) versions (DIFF_POD12, DIFF_POD11, and DIFF_POD10) use complementary single-ended drivers for outputs and differential receivers for inputs.

Table 5. Allowed Attributes for DIFF_POD12, DIFF_POD11, and DIFF_POD10 I/O Primitives
Attributes IBUFDS/IBUFDSE3 IOBUF/IOBUFE3 OBUFDS/OBUFTDS
Allowed Values Allowed Values Allowed Value
IOSTANDARD DIFF_POD12,DIFF_POD11, DIFF_POD10 DIFF_POD12,DIFF_POD11,DIFF_POD10 DIFF_POD12,DIFF_POD11, DIFF_POD10
SLEW N/A FAST (Default), MEDIUM, SLOW FAST (Default), MEDIUM, SLOW
OUTPUT_IMPEDANCE N/A RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60 RDRV_40_40 (Default), RDRV_48_48, RDRV_60_60
ODT RTT_40 (Default), RTT_48, RTT_60, RTT_NONE RTT_40 (Default), RTT_48, RTT_60, RTT_NONE N/A
PRE_EMPHASIS N/A RDRV_240, RDRV_NONE (Default) RDRV_240, RDRV_NONE (Default)
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_NONE (Default) CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_NONE (Default) N/A
DQS_BIAS TRUE, FALSE (Default) TRUE, FALSE (Default) TRUE, FALSE (Default)
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3 DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3

MIPI_DPHY

The MIPI D-PHY standard (MIPI_DPHY) is intended for use in mobile devices including cameras, displays, and unified protocol interfaces. MIPI_DPHY leverages the X5PHIO_XCVR_X2 UNISIM which must be the X5IO Wizard IP in the Vivado tools to instantiate the X5IO PHY block.

Table 6. Allowed Attributes for MIPI_DPHY I/O Primitives
Attributes X5PHIO_XCVR_X2
Allowed Values
IOSTANDARD MIPI_DPHY
DIFF_TERM_ADV TERM_100, TERM_NONE (Default)
PRE_EMPHASIS N/A
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default)
LVDS_PRE_EMPHASIS FALSE (Default), TRUE
DC_BIAS DC_BIAS_0, DC_BIAS1, DC_BIAS2, DC_BIAS3

MIPI_CPHY

The MIPI C-PHY standard (MIPI_CPHY) is intended to interface with cameras, displays, and unified protocol interfaces. MIPI_CPHY leverages a pair of X5PHIO_XCVR_X2 UNISIMs which must be the MIPI IP in the Vivado tools to instantiate the X5IO PHY block. A single MIPI_CPHY lane leverages three pins to create a SYMBOL based interface system with an embedded clock. CPHY must be used with the CMPHY Octad and requires a specific pin orientation for a given three-pin grouping (triplet).

Table 7. Allowed Attributes for MIPI_CPHY Primitives
Attributes X5PHIO_XCVR_X2
Allowed Values
IOSTANDARD MIPI_CPHY
CTLE_EQ CTLE_EQ_LEVEL0, CTLE_EQ_LEVEL1, CTLE_EQ_LEVEL2, CTLE_EQ_LEVEL3, CTLE_EQ_LEVEL4, CTLE_EQ_LEVEL5, CTLE_EQ_LEVEL6, CTLE_EQ_LEVEL7, CTLE_EQ_LEVEL8, CTLE_EQ_NONE (Default)
CPHY_TERM_M/S

TRUE

FALSE (Default)

DIFF_UNDEFINED Default IOSTANDARD

When an IOSTANDARD is not defined by the user, the default assignment for the IOSTANDARD defaults to DIFF_UNDEFINED. For an X5IO design to complete implementation, a non-default IOSTANDARD must be defined with one of the valid I/O standards described in this section. The DIFF_UNDEFINED standard acts as a placeholder to allow a design to complete the early stages of implementation.