X5IO IOB Primitives - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2025-03-07
Revision
1.6 English

In addition to the many traditional buffer primitives, the X5IO utilizes a unique primitive type in the IOB, the XCVR_X2. The X5IO introduces the X5PHIO_XCVR_X2 resource which combines IOB and serialization resources for high-speed interfaces. Each X5PHIO_XCVR_X2 accommodates a grouped pin pair and has a dedicated connection to a specific X5IO PHY Octad. For more details on using the X5PHIO_XCVR_X2, see X5IO PHY Resources.

When not using the X5IO CMPHY resources, IOB access is provided through an array of input, output, and bidirectional primitives. Unlike previous architectures, dedicated low-speed I/O logic resources are limited in the X5IO. Register stages adjacent to the IOBs must occur in fabric (BLI or PL).

To aid in high-speed outputs, X5PHIO banks contain a multiplexer on the output stage for non-PHY use cases. When IOB primitives ending in _ODDR (OBUF_ODDR, OBUFT_ODDR, IOBUF_ODDR, IOBUFDS_ODDR, IOBUFDS_DIFF_OUT_IBUFDISABLE_ODDR, OBUDS_DDR) are used, the ODDR MUX structure is present. The ODDR MUX is a 2:1 multiplexer that allows two data signals to be sent to the output based on the stimulus of a clock input. The intended use case is that a register stage in the fabric is used to feed the two inputs (I_0 and I_1) with a toggling clock fed into the C port providing dual-edge switching on an output pin.

Registering Outputs in X5IO

Although many of the resources are familiar from previous architectures, theAMD Versalâ„¢ AI Edge Series Gen 2 and AMD Versalâ„¢ Prime Series Gen 2 devices introduce a new concept of an ODDR MUX, which incorporates a multiplexer structure into the output buffer allowing two synchronous resources to drive a single IOB. The following figure illustrates a typical use case for the OBUF_ODDR buffer. The OBUF_ODDR does not include any register resources, but rather a clock-controlled MUX and output buffer.

Figure 1. OBUF_ODDR

The Vivado Design Suite library includes an extensive list of primitives supporting many I/O primitives. These primitives are also described in the sections below. The generic primitives can each support most of the single-ended I/O standards:

  • IBUF
  • IBUFE3
  • IOBUF
  • IOBUFE3
  • IOBUF_ODDR
  • OBUF
  • OBUFT
  • OBUF_ODDR
  • OBUFT_ODDR
  • KEEPER
  • PULLDOWN
  • PULLUP
  • X5PHIO_XCVR_X2 (described in X5IO PHY Resources)

These generic primitives can each support most of the available differential I/O standards:

  • IBUFDS
  • IBUFDSE3
  • IBUFDS_DIFF_OUT
  • IOBUFDS
  • IOBUFDS_ODDR
  • IOBUFDSE3
  • IOBUFDS_DIFF_OUT
  • IOBUFDS_DIFF_OUT_IBUFDISABLE
  • IOBUFDS_DIFF_OUT_ODDR
  • IOBUFDS_DIFF_OUT_IBUFDISABLE_ODDR
  • OBUFDS
  • OBUFDS_ODDR
  • X5PHIO_XCVR_X2 (described in X5IO PHY Resources)