The X5IO pins are grouped in banks of 32 IOBs (16 pairs) with each IOB having direct access to the X5IO PHY logic which is used for the integrated DDRMC, soft memory controllers, MIPI (C-PHY and D-PHY) and custom high-performance I/O interfaces. The X5IO only provides access to the PL fabric when bypassing the PHY. There are no dedicated lower-speed registers in the X5IO IOB.
Each IOB in the X5IO shares the same VCCO power supply that is used to power driver logic, receiver logic, and termination. Input, output, and bidirectional interfaces will have a specific VCCO voltage requirement, so care must be taken to ensure that a compatible VCCO level is used for all standards in each X5IO bank.
It is expected that most designs will only need one or two unique VCCO levels for a device. To simplify board design, several packages tie multiple banks together in the package. For example, pins VCCO_700 on a given device might supply banks 700, 701, 702, 703, 704, and 705. For these combined banks, care must be taken to ensure a single voltage is compatible for all X5IO. Though there might only be designators for bank voltages on the package, the IC is still partitioned into 32 pin banks. See the Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) for more details for specific devices.
Corner Banks, PL Only Banks, and Shared NMU Pins
When X5IO banking resources are located adjacent to certain resources such as the processing system (PS) or high-speed transceiver columns, the X5IO bank has limited functionality. While clocking pins (GC) in corner banks have full access to clocking resources, non-clocking pins will be restricted to the memory controller (DDRMC) functionality. Because these restricted X5IO banks are typically located at the corners of a device, they are referred to as corner banks. Though usually defined along bank boundaries, in some instances a partial bank on nibble boundaries might be restricted to DDRMC use. Corner bank locations vary by device and are explicitly called out in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) with a DDRMC designation. In pin planning a Versal device design, it is important to realize that corner banks should only be used for DDRMC interfaces. When using the Advanced I/O Planner for Advanced I/O Wizard designs, the corner banks are blocked from use.
In addition to corner banks (which only have DDRMC functionality), there can be X5IO banks in a device that have PL access but no DDRMC access. A DDRMC can span three X5IO banks. In some devices X5IO banks might exist but do not connect to a DDRMC, often referred to as "PL only" banks. The X5IO in these banks have standard PL access but do not have connections to the DDRMC. It is important to refer to Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013) when planning a layout to ensure a given bank has the necessary function needed.
Besides the DDRMC limitations, some BLIs provide access to the NoC via a NoC Master Unit (NMU). Pins marked as NO_NMU_SHARED would mean these pins have fabric access but the BLI resources are shared with an NMU. As a result, the NMU access point that shares a pin's BLI is unavailable when used as an I/O.