- Banks are located on the bottom periphery of the device.
- Banks are groups of 32 IOBs. Each IOB is capable of both
single-ended and differential signaling.
- In several devices, several banks might share package VCCO pins.
- VREF is internally generated (only). When used
with the X5IO PHY, VREF level is controlled at a per-pin level.
- To save pins and board space, DCI reference resistors are no longer required
on a per bank basis, but rather are shared with many banks.
- Output drive and termination are calibrated against the DCI
reference resistor.
- Supported bank voltages are 1.0V, 1.1V, and 1.2V.
- Output drive strength support for LVCMOS of 4 mA and 8 mA.
- LVDS supported in 1.2V banks.
- MIPI C-PHY supported in 1.2V banks
- The X5IO IOB is accessible via the input/output/bidirectional
primitives or through the XCVR_X2 when used as a PHY.