The X5IO are grouped into 32-pin banks with supporting resources for high-performance interfaces. Each X5IO can use the X5IO PHY to align, serialize, and deserialize a data stream, or the PHY can be bypassed for direct fabric access. The X5IO input and output buffers (IOB) support single-ended and differential I/O standards along with resources to support a high level of signal quality.
- 1.0V, 1.1V, 1.2V bank voltage standards
- X5IO PHY logic resources to align and serialize/deserialize high-speed data streams
- Lower-bandwidth interfaces can bypass the PHY to have direct access to the fabric
- Internally generated VREF support (shared across octad boundaries)
- Calibrated output drive support
- Calibrated internal termination
- Internal differential termination
- Internal bias support
- Transmitter pre-emphasis
- Supports serialization/deserialization ratios of 1:16, 1:8, 1:4, and 1:2
- Receive equalization (CTLE and DFE)