The X5IO PHY can control buffers with tristate capability. The tristating can be performed on a per-bit basis, as determined through the TBYTE_CTL_<0-7> attribute.
Controlling Tristate Control
Buffers with tristate capability can be controlled through the X5IO PHY on a per-BIT basis, as determined through the TBYTE_CTL_<0–7> attribute. The <0–7> suffix of TBYTE_CTL_<0–7> corresponds to the BIT it is applied to. So TBYTE_CTL_0 is the tristate control setting for BIT[0], TBYTE_CTL_1 corresponds to BIT[1], and so on.
TBYTE_CTL_x determines which signal, T or PHY_WREN, is accepted by BIT[x]. For example, if BIT[0] receives both a PHY_WREN and T stimulus, only the one matching TBYTE_CTL_0 is accepted. T_OUT[x] is then the output to the IOB.
- TBYTE_CTL_x = T: Uses the T[x] input of the X5IO PHY to drive the tristate control signal to the IOB of BIT[x]. This is a combinatorial path from the PL and thus is not aligned to TX data. When TX_DATA_WIDTH = 2, this is the only TBYTE_CTL_x setting supported.
- TBYTE_CTL_x = PHY_WREN: Inverts and serializes the PHY_WREN input of the PHY drive (broadcast) through the tristate control signal to the IOB of each BIT. Each bit of PHY_WREN acts as the tristate control signal for two UI worth of data. The serialized and inverted PHY_WREN signal is aligned to the serialized output of the TX datapath O0. PHY_WREN cannot be used when TX_DATA_WIDTH = 2.
The latency through the TX datapath is shown for TBYTE_CTL_x = PHY_WREN. PHY_WREN takes one cycle longer than the data to propagate through the PHY. Due to this, PHY_WREN should be applied one cycle before TX data is presented to the PHY from the PL.
When using TBYTE_CTL = PHY_WREN, the T_OUT routing delays to the IOB are longer than the O0 routing delays as shown in the following figure.