The TX datapath is composed of the following:
- FIFO: The CMPHY_OCTAD adds a 4-deep (8-bit word) transmit FIFO for transmit data.
- Serializer: The serializer supports 16:1, 8:1, 4:1, and 2:1 serialization to the fabric. Serialization is performed across the CMPHY_OCTAD (16:8) and the X5IO PHY_XCVR_X2 (8:1, 4:1, 2:1). Tristate control logic can similarly be serialized using the PHY_WREN ports when TBYTE_CTL_0–7 ≥ PHY_WREN.
- Output Delay: Output delays can delay outgoing serialized data up to 512 taps (0 to 511 taps).
For transmit data the CMPHY_OCTADs FIFO supports 2, 4, 8, or 16-bit data. The transmit FIFO is 10 words (8-bit) deep.
The CMPHY_OCTAD sends parallel data on a dedicated 8-bit interface to the X5IO PHY_XCVR_X2. The 16-bit data is internally sent as two 8-bit transfers.