RX Datapath - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2025-05-22
Revision
1.7 English

The RX datapath is composed of the following:

  • Input Delay: Input delays can delay incoming serialized data up to 512 taps (0–51 taps) and supports cascaded delays.
  • Deserializer: The deserializer supports 1:16, 1:8, 1:4, and 1:2 deserialization to the fabric. Deserialization is performed across the X5IO PHY_XCVR_X2 (1:2, 1:4, 1:8) and CMPHY_OCTAD (8:16).
  • FIFO: The CMPHY_OCTAD contains a 10-deep (8-bit word for 8- and 16-bit data, 4-bit word for 4-bit data, and 2-bit word for 2-bit data) receive FIFO similar to XPHY.

Receive data is supported in the fabric as 2-, 4-, 8-, or 16-bit data. The receive FIFO is 10 words deep.

The CMPHY_OCTAD receives 8-bit data from the X5IO PHY_XCVR_X2 primitive. The 16-bit data is sent to two 8-bit transfers controlled by PHY_RDEN.