X5IO PHY supports unidirectional C-PHY interfaces:
- HS Mode (RX clock recovery)
- LP Mode
- ALP Mode
X5IO PHY adds CPHY receiver circuitry for extracting the embedded clock. To support the embedded clock required for CPHY, the CPHY must be placed in BIT0/BIT1/BIT2 or BIT4/BIT6/BIT7. Any leftover BIT from the XCVR_X2 pair not used for CPHY (BIT3/BIT5) cannot be used. For example, if BIT0/BIT1/BIT2 are used for a CPHY lane, BIT3 can only be used in bypass mode. The following table shows the required mapping of bit location to CPHY pin for a given Octad.
| Octad Pin | C-PHY Interface Pin |
|---|---|
| BIT0 | Line A (interface group A) |
| BIT1 | Line B (interface group A) |
| BIT2 | Line C (interface group A) |
| BIT4 | Line C (interface group B) |
| BIT6 | Line A (interface group B) |
| BIT7 | Line B (interface group B) |
Note: Clock routing from the X5PLL and
recovered CPHY clocks share the same routing resources. As a result, not all X5PLL
outputs are available in CPHY applications.