Differential Input Buffer Primitives - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID: AM010
Release Date: 2025-05-22
Revision: 1.7 English

Figure 1. Differential Input Buffer Primitives

Table 1. IBUFDSE3, IBUFDS, IBUFDS_DIFF_OUT, and IBUFDS_DIFF_OUT_IBUFDISABLE Attributes
Attribute	Values	Description
IBUF_LOW_PWR	TRUE, FALSE	When set to TRUE, allows for reduced power on differential inputs for standards (for example: LVDS). A setting of FALSE demands more power but delivers higher performance characteristics.
IOSTANDARD	See Table 1	Assigns an I/O standard to the element.
DIFF_TERM	TRUE, FALSE	Turns the built-in differential termination on (TRUE) or off (FALSE).
DQS_BIAS	TRUE, FALSE	Provides pull-up/pull-down feature required for some DQS memory interface pins or provides DC bias for certain LVDS applications.
USE_IBUFDISABLE	TRUE, FALSE	Enables the use of the IBUFDISABLE port. (IBUFDSE3, IBUFDS_DIFF_OUT_IBUFDISABLE only)

Table 2. IBUFDSE3, IBUFDS, IBUFDS_DIFF_OUT, and IBUFDS_DIFF_OUT_IBUFDISABLE Ports
Port	I/O	Description
O	Output	Buffer output representing the input path to the device.
OB	Output	Complimentary buffer output representing the input path to the device. (IBUFDS_DIFF_OUT only)
I	Input	Input port connection. Connect directly to top-level P-side port in the design.
IB	Input	Input port connection. Connect directly to top-level N-side port in the design.
IBUFDISABLE	Input	The IBUFDISABLE pin can disable the input buffer and force the O output to the internal logic to a logic-Low when the IBUFDISABLE signal is asserted High. (IBUFE3, IBUFDISABLE,IBUFDS_DIFF_OUT_IBUFDISABLE only)
OSC[3:0]	Input	This is not a supported port and must be left unconnected.
OSC_EN[1:0]	Input	This is not a supported port and must be left unconnected.