Delays - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)

Document ID
AM010
Release Date
2025-05-22
Revision
1.7 English

Three types of delays exist within an X5IO PHY. All delay adjustments must be done through the APB3 interface.

Note: A tap is the smallest amount of delay that a delay line can produce.
  • Input delays: Input delays can delay incoming serialized data up to 512 taps (0–511 taps). The same delay can be configured as quarter delays.
  • Output delays: Output delays can delay outgoing serialized data up to 512 taps (0–511 taps).
  • Quarter (QTR) delays: QTR delays are applied to the p-clk and n-clk. QTR delays can be used up to 512 taps (0–511 taps).

For more information on the p-clk and n-clk, see Clocking.