DQS_BIAS and DC_BIAS - AM010

DQS_BIAS

DQS_BIAS behaves as a logic 0 holding mechanism for undriven pins in pseudo-differential buffers (e.g., DIFF_HSTL or DIFF_SSTL) by weakly pulling the P-side of the buffer to GND and the N-side of the buffer to V_CCO. This allows an IDLE link to maintain a fixed logic level when a driver and termination are disabled on the link. The left circuit in the following figure shows DQS_BIAS behavior on pseudo-differential links.

The allowed values for the DQS_BIAS attribute for applicable I/O standards are TRUE and FALSE (DEFAULT) and are enabled using the following syntax:

set_property DQS_BIAS TRUE|FALSE [get_ports port_name]

DC_BIAS

DC_BIAS provides an internal bias to both P and N pins used as an input in scenarios where an AC-coupled differential signal needs to be re-biased such that the LVDS12 receiver specifications are met. The DC_BIAS feature creates a bias through an equivalent voltage divider network to the bank's V_CCO. The DC_BIAS attribute can be added to the XDC:

set_property DC_BIAS DC_BIAS_0|DC_BIAS_1|DC_BIAS_2|DC_BIAS_3 [get_ports port_name]

The DC_BIAS_1 setting provides the equivalent to 192 Ω at 20% V_CCO. In a 1.2V bank, the combination of DIFF_TERM_ADV and DC_BIAS_1 provide an appropriate termination and bias for an AC-coupled LVDS link without the need for bias or termination components on the PCB. DC_BIAS_2 provides the equivalent of 48Ω to 20% V_CCO, but is not recommended for use with AC coupling due to a higher current draw caused by the voltage divider used to generate the equivalent 48Ω voltage divider. DC_BIAS_3 provides a 50Ω to GND bias which has very limited practical use as a bias network. With an LVDS12 IOSTANDARD used in a 1.2V bank, the combination of DC_BIAS_1 and DIFF_TERM_ADV provide both a bias and termination appropriate for many differential signals that require AC coupling. Because DC_BIAS can corrupt a weaker driver, it should not be used when the IOB is configured as an output or bidirectional.