CMPHY_OCTAD - AM010

Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010)
Document ID
AM010
Release Date
2025-05-22
Revision
1.7 English

The following table describes the ports on the CMPHY_OCTAD. Ports that are being described for simulation purposes and are only used within the X5IO PHY primitives are listed as X5IO PHY input and X5IO PHY output.

Table 1. CMPHY_OCTAD Ports
Port Name Width Input/Output Clock Domain Description
DLY_RDY   Output   Indicates that delay lines can now be changed. Internal calibration of PHY is complete and ready for external calibration for VT compensation.
DYN_DCI_IN [7:0] Input   DYN_DCI controls turning off/on receiver termination for BIT[x]. A calibration state machine must be used to configure the X5IO PHY to enable dynamic DCI.
IBUFDISABLE [7:0] Input   When IBUF_DISABLE_SRC_<0-7> = EXTERNAL, disables the input buffer when IBUFDISABLE is asserted High.
PADDR [9:0] Input PCLK APB3 address.
PCLK   Input PCLK APB3 clock, maximum 300 MHz.
PENABLE   Input PCLK APB3 enable signal indicates second and subsequent cycles of the APB transfer.
PHY_2TO1_CLK   Input   Clock input from fabric for low latency 2 to1 mode.
PHY_CLK   Input   Fabric clock for PHY_D0 to PHY_D7, PHY_WREN, PHY_WRCS, PHY_RDEN, and PHY_RDCS. This interface clock should be timed with zero cycle constraints for best write path latency.
PHY_D0 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[0]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ0 pin.
PHY_D1 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[1]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ0 pin.
PHY_D2 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[2]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ1 pin.
PHY_D3 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[3]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ1 pin.
PHY_D4 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[4]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ2 pin.
PHY_D5 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[5]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ2 pin.
PHY_D6 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[6]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ3 pin.
PHY_D7 [15:0] Input PHY_CLK TX data from the programmable logic for BITSLICE[7]. Parallel data (2/4/8/16) is combined with tristate data and transmitted to the XCVR_X2 on the PHY2XCV_WR_DQ3 pin.
PHY_FIFO_EMPTY [1:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RXF_FIO_WRCLK in BYPASS mode PHY_FIFO_EMPTY[0] is the receiver FIFO empty status.
PHY_FIFO_RDEN [1:0] Input RX_FIFO_RDCLK PHY_FIFO_RDEN[0] used for receiver FIFO read enable clocked by RX_FIFO_RDCLK[0]. PHY_FIFO_RDEN[1] is reserved for future use.
PHY_KEEPER_EN [7:0] Input   Unused.
PHY_LP_I_0 [3:0] X5IO PHY Output   P-side LP receiver or cmos receiver output.
PHY_LP_I_1 [3:0] X5IO PHY Output   N-side I/O LP receiver or cmos receiver output.
PHY_LP_RX_DIS_OR_TERM_EN [3:0] Input   Reserved for future use.
PHY_LP_TX_O_0 [3:0] Input   Reserved for future use.
PHY_LP_TX_O_1 [3:0] Input   Reserved for future use.
PHY_LP_TX_T [3:0] Input   Reserved for future use.
PHY_PD   Output async TX FIFO phase detector signal. This is an AND of the four TX FIFO phase detector outputs. Used by X5IO Wizard and the X5PLL phase shift interface to optimize the phases of the X5PLL.
PHY_Q0 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[0]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(0).
PHY_Q1 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[1]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(0).
PHY_Q2 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[2]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(1).
PHY_Q3 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[3]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(1).
PHY_Q4 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[4]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(2).
PHY_Q5 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[5]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(2).
PHY_Q6 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[6]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(3).
PHY_Q7 [15:0] Output RX_FIFO_RDCLK in SYNC and ASYNC modes. RX_FiFO_WRCLK in BYPASS mode Read data from xcvr BIT[7]. Clocked by clb2phy_rxfifo_rdclk (single cycle path). From xcvr_x2(3).
PHY_RDCS0 [7:0] Input PHY_CLK Read chip select bits for cs0, for all cmphy_octad. Clocked by clb2phy_clk.
PHY_RDCS1 [7:0] Input PHY_CLK Read chip select bits for cs1, for all cmphy_octad. Clocked by clb2phy_clk.
PHY_RDEN [7:0] Input PHY_CLK PHY_RDEN controls the gating of the capture clock for the Octad based on CONTINUOUS_DQS, RX_GATING, and RX_DATA_WIDTH settings. Always ensure the strobe has stabilized and BISC has completed before asserting PHY_RDEN. When RX_GATING = ENABLE, and CONTINUOUS_DQS = TRUE, the four bits of PHY_RDEN are OR'd together and that output is used to control the gate. Capture clock is enabled if PHY_RDEN > 0. PHY_RDEN contains a 2-stage synchronizer when CONTINUOUS_DQS = TRUE requiring up to three capture clock cycles. When RX_DATA_WIDTH = 4 or 8, RX_GATING = ENABLE, and CONTINUOUS_DQS = FALSE, set the following bits of PHY_RDEN to 1 to accept the strobe or 0 to reject the strobe. PHY_RDEN is synchronized to PLL_CLK for this attribute combination. Each bit of PHY_RDEN controls two UI worth of data:
  • If RX_DATA_WIDTH = 8: [3:0]
  • If RX_DATA_WIDTH = 4: [2][0]
  • If RX_DATA_WIDTH = 2: not supported

When RX_GATING = DISABLE, the gate is always open, regardless of the value of RX_DATA_WIDTH, CONTINUOUS_DQS, or PHY_RDEN. When SERIAL_MODE = TRUE, tie all four bits High. When the interface is only TX, tie PHY_RDEN to 0. See Bidirectional Datapath for more information.
PHY_RDY   Output   X5IO PHY is ready for VT compensation.
PHY_RST   Input   Asynchronous reset for clb2phy_clk logic.
PHY_RXFIFO_RDCLK [1:0] Input - Fabric input. PHY_RXFIFO_RDCLK[0] is the receiver's FIFO clock. PHY_RXFIFO_RDCLK[1] is reserved for future use.
PHY_STATUS   Output   PHY status, multimode. RX gate phase, or slave mode write leveling CK to DQS phase.
PHY_WRCS0 [7:0] Input PHY_CLK Write chip select bits for cs1, for all cmphy_octad. Clocked by clb2phy_clk.
PHY_WRCS1 [7:0] Input PHY_CLK Write chip select bits for cs1, for all cmphy_octad. Clocked by clb2phy_clk.
PHY_WREN [7:0] Input PHY_CLK Write enable for all cmphy_octad. Clocked by clb2phy_clk.
PHY2XCV_DYNAMIC_DQ_TS   X5IO PHY Output   XCVR_X2 Dynamic DCI control signal.
PHY2XCV_IBUF_DIS_OR_HS_RX_DIS [7:0] X5IO PHY Output   Reserved
PHY2XCV_RD_CTL0 [7:0] X5IO PHY Output XCV2PHY_WR_CLK0 Connects to XCVR_X2_0. DQS gating and rank switching control to xcvr_x2(0).
PHY2XCV_RD_CTL1 [7:0] X5IO PHY Output XCV2PHY_WR_CLK1 Connects to XCVR_X2_1. DQS gating and rank switching control to xcvr_x2(1).
PHY2XCV_RD_CTL2 [7:0] X5IO PHY Output XCV2PHY_WR_CLK2 Connects to XCVR_X2_2. DQS gating and rank switching control to xcvr_x2(2).
PHY2XCV_RD_CTL3 [7:0] X5IO PHY Output XCV2PHY_WR_CLK3 Connects to XCVR_X2_3. DQS gating and rank switching control to xcvr_x2(3).
PHY2XCV_WR_CTL0 [7:0] X5IO PHY Output XCV2PHY_WR_CLK0 Connects to XCVR_X2_0. Clock gating and rank switching control to xcvr_x2(0).
PHY2XCV_WR_CTL1 [7:0] X5IO PHY Output XCV2PHY_WR_CLK1 Connects to XCVR_X2_1. Clock gating and rank switching control to xcvr_x2(1).
PHY2XCV_WR_CTL2 [7:0] X5IO PHY Output XCV2PHY_WR_CLK2 Connects to XCVR_X2_2. Clock gating and rank switching control to xcvr_x2(2).
PHY2XCV_WR_CTL3 [7:0] X5IO PHY Output XCV2PHY_WR_CLK3 Connects to XCVR_X2_3. Clock gating and rank switching control to xcvr_x2(3).
PHY2XCV_WR_DQ0 [31:0] X5IO PHY Output XCV2PHY_WR_CLK0

[31:24] = Tristate to xcvr_x2(0) bit 1.

[23:16] = Write data or CA/CK to xcvr_x2(0) bit 1.

[15:8] = Tristate to xcvr_x2(0) bit 0.

[7:0] = Write data or CA/CK to xcvr_x2(0) bit 0.
PHY2XCV_WR_DQ1 [31:0] X5IO PHY Output XCV2PHY_WR_CLK1

[31:24] = Tristate to xcvr_x2(1) bit 1.

[23:16] = write data or CA/CK to xcvr_x2(1) bit 1.

[15:8] = Tristate to xcvr_x2(1) bit 0.

[7:0] = Write data or CA/CK to xcvr_x2(1) bit 0.
PHY2XCV_WR_DQ2 [31:0] X5IO PHY Output XCV2PHY_WR_CLK2

[31:24] = Tristate to xcvr_x2(2) bit 1.

[23:16] = Write data or CA/CK to xcvr_x2(2) bit 1.

[15:8] = Tristate to xcvr_x2(2) bit 0.

[7:0] = Write data or CA/CK to xcvr_x2(2) bit 0.
PHY2XCV_WR_DQ3 [31:0] X5IO PHY Output XCV2PHY_WR_CLK3

[31:24] = Tristate to xcvr_x2(3) bit 1.

[23:16] = Write data or CA/CK to xcvr_x2(3) bit 1.

[15:8] = Tristate to xcvr_x2(3) bit 0.

[7:0] = Write data or CA/CK to xcvr_x2(3) bit 0.
PRDATA [15:0] Output PCLK APB3 read data driven when pwrite is Low.
PREADY   Output PCLK APB3 ready signal used to extend the transfer.
PRESETN   Input - APB3 active-Low reset synchronized to pclk within CmPHY_octad and xcvr_x2.
PSEL   Input PCLK APB3 slave device selected and data transfer required.
PSLVERR   Output PCLK APB3 slave error signal. Always Low. X5IO PHY does not generate APB errors.
PWDATA [15:0] Input PCLK APB3 write data driven when pwrite is High.
PWRITE   Input PCLK APB3 asserted for write and negate for read.
RIU2XCV_CA0   X5IO PHY Output RIU2XCV_CK0 Serial RIU Interface. Connect to XCVR_X2_0. Command and address.
RIU2XCV_CA1   X5IO PHY Output RIU2XCV_CK1 Serial RIU Interface. Connect to XCVR_X2_1. Command and address.
RIU2XCV_CA2   X5IO PHY Output RIU2XCV_CK2 Serial RIU Interface. Connect to XCVR_X2_2. Command and address.
RIU2XCV_CA3   X5IO PHY Output RIU2XCV_CK3 Serial RIU Interface. Connect to XCVR_X2_3. Command and address.
RIU2XCV_CK0   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_0. Clock
RIU2XCV_CK1   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_1. Clock
RIU2XCV_CK2   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_2. Clock
RIU2XCV_CK3   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_3. Clock
RIU2XCV_RST0   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_0. Asynchronous reset.
RIU2XCV_RST1   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_1. Asynchronous reset.
RIU2XCV_RST2   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_2. Asynchronous reset.
RIU2XCV_RST3   X5IO PHY Output - Serial RIU Interface. Connect to XCVR_X2_3. Asynchronous reset.
RIU2XCV_WR0   X5IO PHY Output RIU2XCV_CK0 Serial RIU Interface. Connect to XCVR_X2_0. Write data.
RIU2XCV_WR1   X5IO PHY Output RIU2XCV_CK1 Serial RIU Interface. Connect to XCVR_X2_1. Write data.
RIU2XCV_WR2   X5IO PHY Output RIU2XCV_CK2 Serial RIU Interface. Connect to XCVR_X2_2. Write data.
RIU2XCV_WR3   X5IO PHY Output RIU2XCV_CK3 Serial RIU Interface. Connect to XCVR_X2_3. Write data.
RX_RST [7:0] Input   Reserved. Leave unconnected.
RXFIFO_WR_CLK [1:0] Output   Optional divided clock driven by DQS clock. RXFIFO_WR_CLK[0] is the receiver FIFO write clock output. RXFIFO_WR_CLK[1] is reserved for future use.
SEQ_DONE   Output   Sequence done status output
SEQ_DON_I   Input   Sequence done inputs from four Octads within the same bank. Intra-Octad communication.
T [7:0] Input   Combinatorial tristate control when TBYTE_CTRL_<7-0> = T. Outputs are put into tristate when 1.
TX_RST [7:0] Input - Reserved. Leave unconnected.
VT_DLY_IN0 [20:0] Input   Calibration VT Delay intra-Octad communication.
VT_DLY_IN1 [20:0] Input   Calibration VT Delay intra-Octad communication.
VT_DLY_IN2 [20:0] Input   Calibration VT Delay intra-Octad communication.
VT_DLY_IN3 [20:0] Input   Calibration VT Delay intra-Octad communication.
VT_DLY_OUT [20:0] Output   Calibration VT Delay Data
VT_DRFT_IN0 [20:0] Input   Calibration VT Drift intra-Octad communication.
VT_DRFT_IN1 [20:0] Input   Calibration VT Drift intra-Octad communication.
VT_DRFT_IN2 [20:0] Input   Calibration VT Drift intra-Octad communication.
VT_DRFT_IN3 [20:0] Input   Calibration VT Drift intra-Octad communication.
VT_DRFT_OUT [20:0] Output   Calibration VT Drift Data
XCV2PHY_RD_CLK0 [1:0] X5IO PHY Input  
  • [1] = clock (NDQS/4) for read data[15:8] from xcvr_x2(0) bit 1.
  • [0] = clock (NDQS/4) for read data [ 7:0] from xcvr_x2(0) bit 0.
XCV2PHY_RD_CLK1 [1:0] X5IO PHY Input  
  • [1] = clock (NDQS/4) for read data[15:8] from xcvr_x2(1) bit 1.
  • [0] = clock (NDQS/4) for read data [ 7:0] from xcvr_x2(1) bit 0.
XCV2PHY_RD_CLK2 [1:0] X5IO PHY Input  
  • [1] = clock (NDQS/4) for read data[15:8] from xcvr_x2(2) bit 1.
  • [0] = clock (NDQS/4) for read data [ 7:0] from xcvr_x2(2) bit 0.
XCV2PHY_RD_CLK3 [1:0] X5IO PHY Input  
  • [1] = clock (NDQS/4) for read data[15:8] from xcvr_x2(3) bit 1.
  • [0] = clock (NDQS/4) for read data [ 7:0] from xcvr_x2(3) bit 0.
XCV2PHY_RD_DQ0 [15:0] X5IO PHY Input XCV2PHY_RD_CLK0
  • [15:8] = read data from xcvr_x2(0) bit 1.
  • [7:0] = read data from xcvr_x2(0) bit 0.
XCV2PHY_RD_DQ1 [15:0] X5IO PHY Input XCV2PHY_RD_CLK1
  • [15:8] = read data from xcvr_x2(1) bit 1.
  • [7:0] = read data from xcvr_x2(1) bit 0.
XCV2PHY_RD_DQ2 [15:0] X5IO PHY Input XCV2PHY_RD_CLK2
  • [15:8] = read data from xcvr_x2(2) bit 1.
  • [7:0] = read data from xcvr_x2(2) bit 0.
XCV2PHY_RD_DQ3 [15:0] X5IO PHY Input XCV2PHY_RD_CLK3
  • [15:8] = read data from xcvr_x2(3) bit 1.
  • [7:0] = read data from xcvr_x2(3) bit 0.
XCV2PHY_WR_CLK0   X5IO PHY Input   Clock for write data and read/write control (clock and DQS gating). Clock rate DDR/8. To xcvr_x2(0).
XCV2PHY_WR_CLK1   X5IO PHY Input   Clock for write data and read/write control (clock and DQS gating). Clock rate DDR/8. To xcvr_x2(1).
XCV2PHY_WR_CLK2   X5IO PHY Input   Clock for write data and read/write control (clock and DQS gating). Clock rate DDR/8. To xcvr_x2(2).
XCV2PHY_WR_CLK3   X5IO PHY Input   Clock for write data and read/write control (clock and DQS gating). Clock rate DDR/8. To xcvr_x2(3).
XCV2RIU_CK0   X5IO PHY Input   Serial RIU Interface. Connect to XCVR_X2_0. Read clock.
XCV2RIU_CK1   X5IO PHY Input   Serial RIU Interface. Connect to XCVR_X2_1. Read clock.
XCV2RIU_CK2   X5IO PHY Input   Serial RIU Interface. Connect to XCVR_X2_2. Read clock.
XCV2RIU_CK3   X5IO PHY Input   Serial RIU Interface. Connect to XCVR_X2_3. Read clock.
XCV2RIU_RD0 [3:0] X5IO PHY Input XCV2RIU_CK0 Serial RIU Interface. Connect to XCVR_X2_0. Read data.
XCV2RIU_RD1 [3:0] X5IO PHY Input XCV2RIU_CK1 Serial RIU Interface. Connect to XCVR_X2_1. Read data.
XCV2RIU_RD2 [3:0] X5IO PHY Input XCV2RIU_CK2 Serial RIU Interface. Connect to XCVR_X2_2. Read data.
XCV2RIU_RD3 [3:0] X5IO PHY Input XCV2RIU_CK3 Serial RIU Interface. Connect to XCVR_X2_3. Read data.
Table 2. CMPHY_OCTAD Attributes
Attribute Type Values Default Description
ACC_WAIT_0 BINARY 4'b0000 to 4'b1111 4'b0000  
APBCLK_FREQ INTEGER 0 to 500 100 APB Clock Frequency [MHz]
CAL_DQS_SRC STRING EXTERNAL, INTERNAL EXTERNAL
  • INTERNAL: Set to INTERNAL if the capture clock is sourced from the OCTAD.
  • EXTERN: Set to EXTERNAL if the capture clock comes from a different Octad.
CAL_REFCLK_EN BINARY 2'b00, 2'b01, 2'b10 2'b00 Reserved.
CAL_VT_OFST_C STRING C_DUMMY1, C_DUMMY2 C_DUMMY1 Reserved.
CAL_VT_OFST_EN STRING EN_DUMMY1, EN_DUMMY2 EN_DUMMY1 Reserved.
CAL_VT_OFST_M0 BINARY 10'h000 to 10'h3FF 10'h3FF Reserved.
CAL_VT_OFST_M1 BINARY 10'h000 to 10'h3FF 10'h3FF Reserved.
CAL_VT_SRC STRING OCTAD0, OCTAD1, OCTAD2, OCTAD3 OCTAD0 Reserved.
CLB_CLK_DBL_DCC BINARY 3'b000 to 3'b111 3'b000 Reserved.
CLK_SRC BINARY 0 to 1 1 Reserved.
CLOCK_FREQ DECIMAL 200 to 4320 200 Frequency [MHz] of PLL_CLK0, PLL_CLK90 (X5PHIO_XCVR_X2).
CONTINUOUS_DQS STRING FALSE, TRUE FALSE When set to TRUE, the PHY_RDEN port is used to open/close the dqs gate with a two-stage synchronizer clocked by DQS_CLK. RX_GATING must be set to ENABLE.
DMC_APB_SEL STRING FALSE, TRUE FALSE Reserved for X5IO Wizard.
DMC_BIT_SEL_<0-7> STRING FALSE, TRUE FALSE Reserved. Select line for PHY2XCV_WR_DQ<0-7>. Set to TRUE when DMC is used. Set to FALSE for fabric interfaces where PHY_D<0-7> will be used.
DMC_CTL_SEL STRING FALSE, TRUE FALSE Reserved. Routing setting used to select line for bitslice controls. Set to TRUE when DMC is used. Set to FALSE for fabric interfaces to enable PHY_RDEN, PHY_RDCS<1-0>, PHY_WREN, PHY_WRCS<1-0>. When set to TRUE, CMPHY_OCTAD DMC control interface is used. Select line for PHY2XCVR_RD_CTL<>, PHY2XCVR_WR_CTL RDEN/PHY_RD_CS0/1/WREN/WRCS Fabric PHY_RDCS0/1, PHY_WRCS0/1, PHY_RDEN, PHY_WREN DMC DMC_RDCS0/1, DMC_WRCS0/1, DMC_RDEN, DMC_WREN.
DQS_MODE BINARY 3'b000 to 3'b111 3'b001 Internal use only.
EN_CK90_CAL STRING FALSE, TRUE FALSE Reserved. Calibration for PLL_CLK90.
EN_DCC_CAL STRING FALSE, TRUE FALSE Reserved. Used for Duty Cycle Correction using X5PHIO_DCCINVBUF.
EN_FIX_DELAY_CAL STRING FALSE, TRUE FALSE Enable Fixed delay calibration.
EN_PRIMARY_DLL_CAL STRING FALSE, TRUE FALSE Reserved.
EN_SEQ_CAL STRING FALSE, TRUE FALSE Reserved.
FD_NORD BINARY 1'b0, 1'b1 1'b0  
GT_VT_SRC STRING INTERNAL, EXTERNAL INTERNAL Reserved.
GT_VT_SRC_OCTAD STRING OCTAD0, OCTAD1, OCTAD2, OCTAD3 OCTAD0 Reserved.
HISTO_DELTA_ADJ BINARY 13'b0_0000_0000_0000 to 13'b1_1111_1111_1111 13'b0_0000_0000_0000 Reserved.
HISTO_F0_TH BINARY 10'b00_0000_0000 to 10'b11_1111_1111 10'b00_0000_0000 Reserved.
HISTO_F1_TH BINARY 10'b00_0000_0000 to 10'b11_1111_1111 10'b00_0000_0000 Reserved.
HISTO_NO_RU STRING FALSE, TRUE FALSE Reserved.
HISTO_NPI_NS BINARY 7'b000_0000 to 7'b111_1111 7'b000_0000 Reserved.
HISTO_R0_TH BINARY 10'b00_0000_0000 to 10'b11_1111_1111 10'b00_0000_0000 Reserved.
HISTO_R1_TH BINARY 10'b00_0000_0000 to 10'b11_1111_1111 10'b00_0000_0000 Reserved.
IBUF_DIS_EXT_SRC_<0-7> STRING FALSE, TRUE FALSE Reserved.
IBUF_DIS_SRC_<0-7> STRING EXTERNAL, INTERNAL EXTERNAL EXTERNAL: IBUF_DISABLE is controlled by PL INTERNAL: IBUF_DISABLE is controlled by X5PHIO circuitry (PHY_RDEN, RD_IDLE_COUNT)
LEG_F_HISTO_E STRING FALSE, TRUE FALSE Reserved.
LEG_F_LGY_E STRING FALSE, TRUE FALSE Reserved.
MIPI_ALPRX_EN_M STRING FALSE, TRUE FALSE Not supported.
MIPI_ALPRX_EN_S STRING FALSE, TRUE FALSE Not supported.
NQTR_DELAY_VALUE_<0-7> BINARY 16'b0000 to 16'hFFFF 16'b0000 Reserved for X5IO Wizard. Delay line used to delay the negative edge capture clock (clock centering).
O_DELAY_VALUE_<0-7> BINARY 16'h0000 to 16'hFFFF 16'b0000 Output delay in ps.
PDL_HISTOGRAM_MODE STRING ENABLE DISABLE DISABLE Reserved.
PDL_CASCADE STRING FALSE, TRUE FALSE Reserved.
PQTR_DELAY_VALUE_<0-7> STRING 16'h0000 to 16'hFFFF 16'b0000 Reserved for X5IO Wizard. Delay line used to delay the positive edge capture clock (clock centering).
PRIMARY_DLL_CONFIG STRING MODEA, MODEB1, MODEB2 MODEA Reserved for X5IO Wizard.
RIUCLK_DBLR_BYPASS STRING FALSE, TRUE FALSE Reserved.
RIU_CLK_DBL_DCC BINARY 3'b000 TO 3'b111 3'b000 Reserved
ROUTETHRU_<0-7> STRING TRUE, FALSE TRUE When TRUE, X5PHIO logic is bypassed.
RX_CLOCK_ALIGN STRING RX_CLOCK_ALIGN_NONE, CLK90_TEST, CLOCK_CNTR, DATA_CNTR, DQS_DELAYED, DQS_NON_DELAYED RX_CLOCK_ALIGN_NONE Defines capture clock to data alignment.
RX_DATA_WIDTH DECIMAL 8, 2, 4, 16 8 Deserialization ratio 1:16, 1:8, 1:4, 1:2.
RXFIFO_MODE_<0-7> STRING ASYNC, BYPASS, SYNC ASYNC Receiver FIFO mode setting for BIT[7:0].
  • ASYNC: Set to ASYNC if the read and write clocks of the FIFO are the same frequency but phase independent.
  • SYNC: Set to SYNC if the read and write clocks of the FIFO are the same clock. SYNC requires a continuous receive data clock.
  • BYPASS: Set to BYPASS for the FIFO to forward the data to the fabric (it is not stored in the FIFO like in the ASYNC and SYNC settings). A zero cycle path is possible here. BYPASS requires a continuous receive data clock.
RXFIFO_WRCLK_SEL STRING CLK0, CLK1, CLK2, CLK3, CLK4, CLK5, CLK6, CLK7 CLK0 Selects which BIT is used as the source for RXFIFO_WR_CLK.
RX_PATH_RESET STRING ENABLE DISABLE DISABLE Reserved.
SA_OFST_CAL_<0-7> STRING SA_OFST_NONE, SA_OFST_AUTO, SA_OFST_MANUAL SA_OFST_NONE Reserved for X5IO Wizard.
SEQ_DIS<0 -7> STRING FALSE, TRUE FALSE Reserved for X5IO Wizard
SEQ_DONE_MASK BINARY 4'b0000, 4'b0011, 4'b1100, 4'b1111 4'b0000 Reserved for X5IO Wizard.
SEQ_DQS_CENTER BINARY 2'b00 to 2'b11 2'b00 Reserved
SEQ_HISTOGRAM_MODE STRING ENABLE, DISABLE DISABLE Reserved
SLEW_MODE STRING MODE0, MODE1, MODE2, MODE3 MODE0 Reserved
TBYTE_CTL_<0-7> STRING T, PHY_WREN T
  • T: Set to T if using the T input (combinatorial path from the PL) as the tristate control signal for BIT[x]. If TX_DATA_WIDTH = 2, only T (not PHY_WREN) can be used as the tristate control signal.
  • PHY_WREN: Set to PHY_WREN if using the PHY_WREN input as the tristate control signal. The serialized and inverted PHY_WREN is synchronized with the TX data. Each bit of PHY_WREN controls the tristate for two bits of data.
TX_DATA_WIDTH DECIMAL 8, 2, 4, 16 8 Determines the serialization factor. In other words, 2:1 / 4:1 / 8:1 / 16:1.
TX_INIT_<0-7> STRING FALSE, TRUE FALSE
  • 1'b0: Sets the TX IOB value during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0.
  • 1'b1: Sets the TX IOB value during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.
TX_INIT_T STRING FALSE, TRUE FALSE
  • 1'b0: Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b0.
  • 1'b1: Sets the tristate control signal during configuration and reset (in this case, TX_RST[x] = 1 or RST = 1) to 1'b1.
VTC_NOT_SPD STRING FALSE, TRUE FALSE Reserved.
WR_CTL_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved.
WR_DQ0_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved.
WR_DQ1_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved.
WR_EN0_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved.
WR_EN1_MUXSEL BINARY 8'b00000000 to 8'b11111111 8'b00000000 Reserved.
WREN_CS_OVERRIDE_<0-7> STRING FALSE, TRUE FALSE Reserved.