The X5IO PHY replaces the RIU fabric interface with the industry standard APB-3 interface for all fabric accesses. Using the APB-3 interface, the different X5IO PHY primitives can be accessed as shown in the following table. Fabric access to the APB-3 interface is shared with the dedicated memory interfaces. As a result, the APB interface is not available when the dedicated memory interfaces are used.
| APB-3 Address | X5IO PHY Block |
|---|---|
| 000 – 03F | CMPHY_OCTAD + X5PHIO_XCVR_X0 |
| 080 – 0BF | CMPHY_OCTAD + X5PHIO_XCVR_X1 |
| 100 – 13F | CMPHY_OCTAD + X5PHIO_XCVR_X2 |
| 180 – 1BF | CMPHY_OCTAD + X5PHIO_XCVR_X3 |
| 040 – 07F | X5PHIO_XCVR_X0 |
| 0C0 – 0FF | X5PHIO_XCVR_X1 |
| 140 – 17F | X5PHIO_XCVR_X2 |
| 1C0 – 1FF | X5PHIO_XCVR_X3 |
| 200 – 3FF | CMPHY_OCTAD |
The following diagrams give examples of a simple APB-3 read transfer and APB-3 write transfer. X5IO PHY requires wait states and holds PREADY Low while processing the APB transfer.
In the read transfer, the second cycle PENABLE is asserted along with the address (PADDR) to be read. The APB read transfer is then sent to the addressed primitives using a high-speed serial RIU interface which can vary from 1 to 23 clock cycles to read back the information. PREADY asserts after the read data (PRDATA) is available.
For write transfers, the address (PADDR) and data (PWRDATA) are processed over two cycles. PREADY asserts when the write transfer has been processed. The APB write transfers are then sent to the appropriate X5IO PHY block using the high-speed serial RIU interface which can take from 1 to 23 clock cycles after PREADY asserts.