Clocking Structure - Clocking Structure - AM009

Versal Adaptive SoC AI Engine Architecture Manual (AM009)

Document ID
AM009
Release Date
2026-02-18
Revision
1.4 English

Each AI Engine tile and interface tile contains a clock-gate control register. This register controls the clock for all AI Engine tiles located above it in the same column, without affecting the clock of the tile itself. When none of the AI Engine tiles above a specific row in a column are in use, you can disable their clock through the control register in the topmost active tile to reduce the power consumption of the AI Engine array.