AI Engine to Programmable Logic Interface - AI Engine to Programmable Logic Interface - AM009

Versal Adaptive SoC AI Engine Architecture Manual (AM009)
Document ID
AM009
Release Date
2026-02-18
Revision
1.4 English

AXI4-Stream switches in the AI Engine to PL tiles can directly communicate with the programmable logic using the AXI4-Stream interface. There are six streams from AI Engine to PL and eight streams from PL to each AI Engine column. From a bandwidth perspective, each AXI4-Stream interface can support the following.

  • 24 GB/s from each AI Engine column to PL
  • 32 GB/s from PL to each AI Engine column

Each stream has a 64-bit interface but can be configured to operate as a 32-bit or 64-bit stream, or two physical streams can be configured to operate as a single 128-bit stream.

Streams from the PL support a subset of the AXI4-Stream protocol:

  • When TLAST = 0, TKEEP is ignored and assumed to be all ones.
  • When TLAST = 1, TKEEP is only supported at 32-bit granularity and valid words must be contiguous:
    • 32-bit streams: TKEEP must be 0xF
    • 64-bit streams: TKEEP can be 0x0F or 0xFF
    • 128-bit streams: TKEEP can be 0x000F, 0x00FF, 0x0FFF, 0xFFFF

In the VC1902 device, there are 50 columns of AI Engine tiles and AI Engine array interface tiles, however, only 39 array interface tiles are available to the PL interface. Therefore, the aggregate bandwidth for PL interface is approximately:

  • 1.0 TB/s from AI Engine to PL
  • 1.3 TB/s from PL to AI Engine

All bandwidth calculations assume a nominal 1 GHz AI Engine clock for the -1L speed grade devices at VCCINT = 0.70V. The number of array interface tiles available to the PL interface and total bandwidth of the AI Engine to PL interface for other devices and across different speed grades is specified in Versal AI Core Series Data Sheet: DC and AC Switching Characteristics (DS957).

The boundary-logic interface flip-flops are between the AI Engine-to-PL interface. They can be used to improve timing. By applying the boundary-logic interface (BLI) constraints to flip-flops in your design, you can automatically take advantage of this feature during design placement. Refer to the AI Engine-PL Interface Techniques for Timing section in Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).