The UltraRAM generates a read access status output (RDACCESS_A/B). This indicates that a read operation is complete and new data is available at the output. This output has the same latency as the corresponding read data. This output can then be used at the top level to select the correct read data when cascading UltraRAMs across multiple columns. When this output is high, it indicates that a read operation executed in that UltraRAM or in a lower UltraRAM that is part of the cascade chain. Crossing columns of cascaded UltraRAMs can require CLB registers to account for pipelining in the column cascade.
The RDACCESS signal supports UltraRAMs that are arranged in a matrix fashion. It identifies which UltraRAM block in a matrix configuration is actively reading data in a given clock cycle. The application can then determine the appropriate read data that needs to be propagated to the final output for processing.
The following figure shows a use case where the RDACCESS signal selects the correct read output data and controls the matrix output data path. The circuit holds the data for the inactive outputs. It is important to match the input delay between the matrix entry point (for example, horizontal pipelining in the fabric for performance reasons) with identical delays on the output side (the delay/pipeline blocks shown in the following figure).