In addition to block RAMs and UltraRAMs, the Versal adaptive SoC includes the following:
- Small 64-bit RAMs distributed throughout the programmable logic.
- Specialized RAMs in the processing system.
- Integrated memory controllers for access to external DDR memories.
Details of these additional memory resources are available in the following documents:
- Refer to the Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005) for small (64-bit) distributed RAMs in the programmable logic.
- Refer to the
Versal
Adaptive SoC Technical Reference Manual (AM011) for
information on the following:
- Processing system on-chip memory (OCM).
- Tightly coupled memories (TCM).
- Accelerator RAM (XRAM), and controller interfaces to external non-volatile memories.
The OCM and XRAM can be accessed from the programmable logic through AXI interfaces.
- Refer to the Versal Adaptive SoC Programmable Network on Chip and Integrated Memory Controller LogiCORE IP Product Guide (PG313) for the integrated memory controller interface to external DDR memories.
Refer to the Versal Architecture and Product Data Sheet: Overview (DS950) for availability and quantities of block RAM, UltraRAM, and additional memory resources in each Versal adaptive SoC.