Shift Registers

Versal® architecture CLB shift registers are very similar to those in used previous architecture CLBs, with the 6-LUT supporting a 32-bit SRL and the 5-LUT/6-LUT pair supporting a pair of 16-bit SRLs. The 32-SRLs can be chained together with a dedicated shift chain using the 6-LUT's SIN and SOUT bel pins. Each slice has an initial SIN shift input and SOUT shift output, and which are connected to the slices in the CLB below and above respectively.

Notable SRL-related changes are in how the SRLs are connected:

• The SIN/SOUT shift chain between slices in a column are broken at the center of the clock regions and the clock region boundaries.
• The LUT6 bel output SOUT connects only to to the following LUT6's SIN input, unlike in previous architecturres where that bel pin also could connected through a site output to interconnect.
• SRL cannot be combined with LUTRAM or with LUT in a slice.
• Inter-LUT shift direction is from A->H, the opposite of previous architectures. The intra-LUT shift direction is still LSB->HSB.
• Support for dual-edge clocking.

SRLs are internally cascadeable in a manner similar to the carry chain. They cascade between logically adjacent LUTs (A_M->B_M->C_M->D_M->E_M->F_M->G_M->H_M) and also between CLBs (H_M->A_M). This enables creation of SRLs of arbitrary lengths. There is no memory cell output to logic like in prior architectures, the SRL output can still reach the interconnect if the read decoder of the last LUT in the chain is used to bring out the SRL output through the LUT output pin. The following figure shows how the LUTs can be cascaded to form long SRL chains.

Figure 1. SRL Cascade

The shift order is from LUT A_M to LUT H_M which is opposite to what was in previous architectures. However, within a LUT the shift order is still the same as in previous architectures.