SRL Shift Register Primitives

Versal ACAP Configurable Logic Block Architecture Manual (AM005)

Document ID: AM005
Release Date: 2023-02-28
Revision: 1.2 English

This example of an SRL shift register primitive is the 32-bit shift register (SRLC32E).

Figure 1. SRL Shift Register Primitive

Attributes

Table 1. Attribute Name, Description, and Possible Values
Attribute	Description	Values
INIT	Specifies logic expression.	64-bit value (hex)
IS_CLK_INVERTED	Specifies whether or not to use the optional inversion on the clock pin (CLK).	1’b0 or 1’b1

Port Descriptions

Table 2. Port Name, Type, and Description
Port	Type	Description
A<4:0>	Input	The address input selects the bit to be read
CE	Input	Active-High clock enable
CLK	Input	Clock
D	Input	SRL data input
Q	Output	SRL data output selected by the address inputs
Q31	Output	SRL data output, provides the last bit value of the 32-bit shift register