The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/14/2025 Version 1.4 | |
| CLB Architecture | Updated to include Versal AI Edge Series Gen2, Premium Series Gen2 and Prime Series Gen2. |
| Differences from Previous Generations | Updated to address CLB types. |
| Differences in Gen2 Devices from Previous Generations | Updated to include Versal AI Edge Series Gen2, Premium Series Gen2 and Prime Series Gen2. |
| CLB Resources | Updated to clarify that there are 2 CLB types. |
| IMUX Register | Updated to include Versal AI Edge Series Gen2, Premium Series Gen2 and Prime Series Gen2. |
| LUTRAM | Updated to include Versal AI Edge Series Gen2, Premium Series Gen2 and Prime Series Gen2. |
| Shift Registers | Updated to include Versal AI Edge Series Gen2, Premium Series Gen2 and Prime Series Gen2. |
| 12/20/2024 Version 1.3 | |
| Figure 2 | Switched what the O5 output pins drive in order to reflect hardware. |
| LUTRAM | Added Address Collision section to clarify that LUTRAM read outputs are from combinatorial logic and do not have address collisions similar to synchronous dual-ported RAMs. |
| Look-Up Table | Added description of the Look-Up table. |
| Carry Logic | |
| 02/28/2023 Version 1.2 | |
| IMUX Register | Added IMUX register restrictions. |
| 04/08/2021 Version 1.1 | |
| IMUX Register | Removed IMUX Control Sets subsection. |
| 07/16/2020 Version 1.0 | |
| Initial release. | N/A |