This chapter provides a detailed view of the AMD Versal™ adaptable computing acceleration platform (adaptive SoCs) configurable logic block (CLB). These details are useful for design optimization and verification, but are not necessary for initiating a design. This chapter includes:
- CLB Resources: An overview of CLB slice features.
- Look-Up Table: A description of the logical function generators.
- Storage Elements: A description of and controls for the latches and flip-flops.
- Carry Logic: Dedicated gates and cascading to implement efficient arithmetic functions.
- Primitives: Overview of the most commonly used CLB primitives.