Look-Up Table

Versal ACAP Configurable Logic Block Architecture Manual (AM005)
Document ID
AM005
Release Date
2023-02-28
Revision
1.2 English
All look-up tables (LUTs) in the configurable logic block (CLB) are 6LUTs. The 6LUT is enhanced with additional multiplexing to enable even more functionality. All features of a LUT are shown in the following figure.
Figure 1. LUT Features

The two multiplexers near the top and bottom of the diagram are new to Versal® architecture. They are static memory cell controlled muxes. These multiplexers are used for the following purposes:

  1. Cascadable LUT -> LUT connections (O6 -> A5)
  2. Enables dual LUT functions of up to six inputs (five in prior architectures)
  3. Used for carry logic paths

These multiplexers select the A5 input by default. They can also be programmed to select no input and in that case their outputs are driven High.

There are four LUT outputs. The prop output is only used for carry logic and is not visible outside the CLB. For standard 6LUT mode, O6 is used as the output. For dual 5LUT mode, O5_1 and O5_2 are both used to bring out the two function outputs to the logic.

Cascade multiplexer paths exist between logically adjacent LUTs in one direction (A->B->C->D->E->F->G->H but not the reverse). The O6 output of one LUT connects through the cascade multiplexer to the A5 pin of the following LUT. The intention is to create a short, fast path between two LUT stages in order to a) reduce delay on critical paths and b) reduce external routing consumption. Optimal use of cascades might result in swapping around LUTs inside a CLB to place critical LUTs next to each other when the penalty to surrounding logic is low. Note that cascade connections are self-contained within a CLB slice (8 LUTs), and do not cross slice boundaries. Also note that the odd connections travel through the carry chain to get to the subsequent LUT. When used as a cascade (and not for carry logic), the carry block is configured such that the prop output is forced to make the carry logic act as a route through for those cascade paths. The following figure is a picture of the cascade connections for one half of the CLB (red arrows). The solid red lines represent actual wires. The dotted red lines represent logical connections that only exist in cascade mode.
Figure 2. Cascade Pattern