Distributed RAM Primitives - AM005

Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005)

Document ID: AM005
Release Date: 2025-05-14
Revision: 1.4 English

Examples are shown for 64-bit single-port and 64-bit dual-port distributed RAM primitives.

Figure 1. RAMS64E5 Distributed RAM Primitive (Single-Port)

Attributes

Table 1. Attribute Name, Description, and Possible Values
Attribute	Description	Values
INIT	Specifies logic expression.	64-bit value (hex)
IS_CLK_INVERTED	Specifies whether or not to use the optional inversion on the clock pin (CLK).	1’b0 or 1’b1

Port Descriptions

Table 2. Port Name, Type, and Description
Port	Type	Description
O	Output	Data output
I	Input	Data input
ADDR0	Input	Address input
ADDR1	Input	Address input
ADDR2	Input	Address input
ADDR3	Input	Address input
ADDR4	Input	Address input
ADDR5	Input	Address input
WE	Input	Write enable
WE2	Input	Additional WE for modes deeper than 64 bits
CLK	Input	Write clock (synchronous)

Figure 2. RAMD64E5 Distributed RAM Primitive (Dual-Port)

Attributes

Table 3. Attribute Name, Description, and Possible Values
Attribute	Description	Values
INIT	Specifies logic expression.	64-bit value (hex)
IS_CLK_INVERTED	Specifies whether or not to use the optional inversion on the clock pin (CLK).	1’b0 or 1’b1

Port Descriptions

Table 4. Port Name, Type, and Description
Port	Type	Description
O	Output	Data output reading from read address
I	Input	Data input
ADDR0	Input	Read address input
ADDR1	Input	Read address input
ADDR2	Input	Read address input
ADDR3	Input	Read address input
ADDR4	Input	Read address input
ADDR5	Input	Write address input
WADR0	Input	Write address input
WADR1	Input	Write address input
WADR2	Input	Write address input
WADR3	Input	Write address input
WADR4	Input	Write address input
WADR5	Input	Write address input
WE	Input	Write address input
WE2	Input	Additional WE for modes deeper than 64 bits
CLK	Input	Write clock (synchronous)