Dual 5LUT mode is supported in Versal® architecture, meaning the carry select and the generate inputs to the carry chain come from the dual 5LUT output pins. Bypass pins no longer feed the carry block. The propagate, sum, and generate functions all are programmed into the LUT. Even LUTs also include the carry select multiplexer. The external carry block only includes carry lookahead multiplexer to accelerate carry propagation delays. Propagate is a sub-function of sum, so an intermediate output (prop) brings the propagate signal out to the carry lookahead logic. There is no longer any dedicated XOR (sum) logic or carry select multiplexer.
The new carry structure is very flexible in terms of carry chain lengths and
starting/end points. Because every cascade multiplexer functions as a carry chain
initialization multiplexer, any LUT can start or end a carry chain.
Figure 1. Carry Chain
