CLB Architecture

The CLB is the main resource in each Versal device and implements programmable combinational logic, sequential logic, and logic paths. These features enable high functionality and routability.

The following figure shows a high-level block diagram of the CLB. There are two CLB types, one with super long line (SLL) connections, and one without. Each CLB contains equal numbers of LUTRAM and SRL-capable LUTs. CLB contains two 4-LUT clusters in SLICEM where {A_M,C_M,E_M,G_M} are part of one cluster, and {B_M,D_M,F_M,H_M} is another.

Note: The programmable logic of the Versal AI Edge Series Gen 2, Premium Series Gen 2, and Versal Prime Series Gen 2 does not include IMUX registers as shown in Figure 1 and Figure 2.

Figure 1. CLB Block Diagram

The following figure shows a Versal device SLICEL/SLICEM. Note the IMUX registers, the carry lookahead logic which now contain fast lookahead multiplexers, and input and output multiplexers before and after the flip-flops. The multiplexers after the flip-flops are new to Versal devices. Some of the inputs to the input multiplexer are from the SLL connections.

Figure 2. SLICEL/SLICEM Block Diagram

CLB Architecture - AM005

Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005)