Versal Adaptive SoC Configurable Logic Block Architecture Manual (AM005) - AM005

Document ID: AM005
Release Date: 2024-12-20
Revision: 1.3 English

Overview
Introduction to Versal Adaptive SoCs
Navigating Content by Design Process
CLB Features
CLB Architecture
Differences from Previous Generations
CLB Resources
Overview
CLB Resources
IMUX Register
Look-Up Table
LUTRAM
Shift Registers
Storage Elements
Control Signals
Carry Logic
Primitives
LUT Primitives
SRL Shift Register Primitives
Distributed RAM Primitives
Carry Look-Ahead Logic Primitives
Additional Resources and Legal Notices
Support Resources
Finding Additional Documentation
Revision History
Please Read: Important Legal Notices

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