Versal AI Edge Series Gen 2 and Versal Prime Series Gen 2 devices contain an X5PLL clocking resource in each X5PHIO bank. The X5PLL is a mixed signal block design to support frequency synthesis, clock network deskew, and jitter reduction. The clock outputs can each have an individual divide, phase shift, and duty cycle based on the same VCO frequency. The primary function of the X5PLL is to support the clocking needs of memory interface IP and X5PHIO I/O interfaces.
All features from XPLL are carried forward into X5PLL. Because all the features are identical to X5PLL, this section only describes any changes from XPLL. The X5PLL has two CLKOUTPHY_0 and CLKOUTPHY_90 output ports dedicated to the PLL_CLK0 and PLL_CLK90 inputs of the X5IO PHY.
Refer to Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for more information on the X5PLL.