X5PLL Ports - X5PLL Ports - AM003

Versal Adaptive SoC Clocking Resources Architecture Manual (AM003)
Document ID
AM003
Release Date
2026-06-09
Revision
1.6 English

The X5PLL has a set of ports specifically for the RIU XPHY interface signals (the X5PLL-RIU interface). These pins can be directly connected to control the interface. For available pins refer to the following tables.

Table 1. X5PLL Ports
Port Name I/O Description
CLKIN Input General clock input.
RST Input Asynchronous reset signal. The RST signal is an asynchronous reset for the X5PLL. The X5PLL synchronously re-enables itself when this signal is released (that is, X5PLL re-enabled). A reset is required when the input clock conditions change (for example, frequency).
PWRDWN Input Powers down instantiated but unused X5PLLs.
CLKOUT[0:3] Output User configurable clock outputs (0 through 3) that can be divided versions of the VCO phase outputs (user controllable) from 2 to 128. The output clocks are phase aligned to each other (unless phase shifted).
CLKOUTPHY_0 Output High-speed clock for X5IO interfaces
CLKOUTPHY_90 Output High-speed clock for X5IO interfaces
CLKOUTPHYEN Input Asynchronous enable of the XPHY clock.
CLKIN1_DESKEW Input Primary clock input to the phase detector 1 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB1_DESKEW Input Secondary (feedback) clock input to the phase detector 1 block for deskewing clock network delays.
CLKIN2_DESKEW Input Primary clock input to the phase detector 2 block for deskewing clock network delays between two different CLKOUT networks.
CLKFB2_DESKEW Input Secondary (feedback) clock input to the phase detector2 block for deskewing clock network delays.
CLKOUTPHY_CASC_IN_0 Input X5PLL CLKOUTPHY_0 cascade input
CLKOUTPHY_CASC_IN_90 Input X5PLL CLKOUTPHY_90 cascade input
CLKOUTPHY_CASC_OUT_0 Output X5PLL CLKOUTPHY_0 cascade output
CLKOUTPHY_CASC_OUT_90 Output X5PLL CLKOUTPHY_90 cascade output
LOCKED Output The LOCKED signal indicates that all functions requiring a LOCKED signal for the X5PLL to operate properly have LOCKED. This LOCKED signal is therefore an AND function of LOCKED_FB and both LOCKED1_DESKEWs, LOCKED2_DESKEWs, if used.
LOCKED_FB Output An output from the X5PLL that indicates when the X5PLL has achieved phase alignment within a predefined window and frequency matching within a predefined PPM range. The X5PLL automatically locks after power on. No extra reset is required. LOCKED is deasserted if the input clock stops or the phase alignment is violated (for example, input clock phase shift). The X5PLL must be reset after LOCKED is deasserted.
LOCKED1_DESKEW

LOCKED2_DESKEW

 Output Indicates if the deskew circuit is locked. Applies only to the deskew circuits used in the design. Ignore these outputs for unused deskew circuits.
DO[15:0] Output The dynamic reconfiguration output bus provides X5PLL data output when using dynamic reconfiguration.
DI[15:0] Input The dynamic reconfiguration data input (DI) bus provides reconfiguration data. When not used, all bits must be set to zero.
DADDR[6:0] Input The dynamic reconfiguration address (DADDR) input bus provides a reconfiguration address for the dynamic reconfiguration. When not used, all bits must be assigned zeros.
DRDY Output The dynamic reconfiguration ready output (DRDY) provides the response to the DEN signal for the X5PLL’s dynamic reconfiguration feature.
DWE Input The dynamic reconfiguration write enable (DWE) input pin provides the write enable control signal to write the DI data into the DADDR address. When not used, it must be tied Low.
DEN Input The dynamic reconfiguration enable (DEN) provides the enable control signal to access the dynamic reconfiguration feature. When the dynamic reconfiguration feature is not used, DEN must be tied Low.
DCLK Input The DCLK signal is the reference clock for the dynamic reconfiguration port.
PSCLK Input Phase shift clock.
PSEN Input Phase shift enable.
PSINCDEC Input Phase shift increment/decrement control.
PSDONE Output Phase shift done.
RIU_CLK Output System clock for RIU interface access.
RIU_ADDR<7:0> Input Address input for the RIU interface.
RIU_WR_DATA<15:0> Output RIU input write data.
RIU_RD_DATA<15:0> Input RIU output read data.
RIU_WR_EN Input When High, enables write to RIU.
RIU_NIBBLE_SEL Input Nibble select to enable RIU read/write.
RIU_VALID Output When High, indicates that last data written is accepted.
  1. All control and status signals except PSINCDEC are active-High.
Tip: The port names generated by the clocking wizard can differ from the port names used on the primitive.