Many of the X5PLL ports are identical to those for the XPLL and MMCM (refer to XPLL Port Descriptions and MMCM Port Descriptions). For dynamic reconfiguration port description, refer to Dynamic Reconfiguration Port (DRP). The additional ports available for the X5PLL are described in this section.
The difference between XPLL and X5PLL is the addition of 90 phase out (CLKOUTPHY_90). The XPHY block produces the 90-degree phase-shifted output for any divide ratio that is chosen. It also makes sure that CLKOUTPHY_90 starts after CLKOUTPHY_0.
Figure 1. CLKOUTPHY Multiplexer Scheme
- CLKOUTPHY_0, CLKOUTPHY_90, and CLKOUTPHYEN
- The X5PLL provides a dedicated CLKOUTPHY_0 and CLKOUTPHY_90 clock outputs to the XPHY. There is special logic associated with these clock outputs to support the synchronization between the programmable logic clock and the XPHY clock generated by the VCO. The PHY-MUX block contains the divider, which can divide-by-1, 2, 4, 8, and 16. This block also synchronizes the assertion and de-assertion of CLKOUTPHYEN to VCO divided by 16 clocks. The block produces the 90-degree phase-shifted output for any chosen divide ratio. It also make sure that CLKOUTPHY_90 starts after CLKOUTPHY_0. CLKOUTPHY_0 and CLKOUTPHY_90 are gated by the CLKOUTPHYEN signal from the programmable logic. When the CLKOUTPHYEN signal is asserted High from the programmable logic, CLKOUTPHY_0 and CLKOUTPHY_90 signals start toggling. The aligns the rising edge with the rising edge of the X5PLL input clock. To make sure that CLKOUTPHY_0 and CLKOUTPHY_90 are aligned with the clock that drives data to XPHY nibbles in an X5IO bank, the data clock must be the same clock as the X5PLL input clock. The CLKOUTPHYEN signal is synchronized to a divide by 16 clock dividers and gates the CLKOUTPHY clock.
- XPHY RIU Interface Pins
- These pins provide a direct connection to the hardened memory controller for highest performance deterministic timing.