For PL Designs, different implementation options are presented by Vivado including Optimization for Power. For designs targeting low power, this setting needs to be selected. It is typical to be able to save up to 30% of the PL power this way, depending on the design contents. Here is a snapshot of the selection in “Implementation Settings” dialog.
More detailed instructions are covered by these guides provide by Xilinx:
https://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/ug786_PowerMethodology.pdf