Set Clock Divider

Zynq UltraScale plus MPSoC Power Management

Release Date: 2023-04-24

Power Optimization Guide for Zynq UltraScale+ MPSoC
Board Design Phase
Device Selection
Device Capacity
Speed Grade
Schematic Design
Impact of Capacitance on PL Power Management
GPIOs for PL Power Management Control
Vivado Design Phase
PS Design Optimizations
PL Design Optimizations
Vivado Options for Power Optimization
Clocks and Power Mode Controls
Software Build & Runtime
Linux Power Management
Bare-Metal Apps using XilPM Library
Custom Software Stack
Debugging Power Management Issues
Child Pages
CPU Power Management
CPU Hotplug
CPU Idle
CPU Frequency Scaling
Related Links
Board Design Considerations for Power Management
Introduction
Power Rail Control
PMUFW Config for Board Power Down
Related Links
DDR Power Optimization
Introduction
DDR Clock Frequency
DDR Bus Width
Clock Stop
Pre-charge Power Down
Interconnect Frequency
Introduction
Configuring Interconnect Frequency
Conclusion
Related Links
Power Down Unused Blocks
Introduction
Using EEMI to power down blocks
Major Power Islands
RPU
GPU
Power Optimization during Boot Up
Introduction
Inspect Clocks and Resets
Inspect Power Islands
Adding Power and Clock controls in FSBL
Optimizing Peripheral Clock Frequencies
Introduction
Optimize Clock Frequencies at Design Phase
Runtime Clock Control
Related Links
Programmable Logic Power Management
Introduction
PL Static Power
PL Dynamic Power
Using PS->PL Clocks
Using PMU GPOs to control power states
Clocking Wizard
Related Links
VCU Power Optimization
Clock Configuration
Encoder/Decoder Settings
Related Links
Debugging Power Management Issues
Introduction
Power Utility Commands
Debugging PMUFW
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 1 - Introduction to the Power Advantage Tool
1 About the Power Advantage Tool
2 Links
3 Prerequisites
4 Power Advantage Tool Sources
4.1 Download the Power Advantage Tool Sources
4.2 Power Advantage Tool Sources Contents
4.2 Power Advantage Tool Sources Contents
5 Xilinx Vivado and SDK
5.1 Install Xilinx Vivado and SDK
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 2 - Installing the Pre-Built Power Advantage Tool
1 Setup
1.2 Hardware Setup
1.3 Creating a Pre-Built SD
1.4 Flashing the MSP430
1.4.1 Flashing the MSP430 with an MSP-FET cable
1.4.2 Flashing the MSP430 without an MSP-FET cable
1.5 Common Setup Issues
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 3 - Running the Pre-Built Power Advantage Tool
1 Release-Specific Instructions
Related Links
Zynq UltraScale+ RFSoC Power Advantage Tool 2020.2 ZCU111
Document History
Power Advantage Tool
Launching the Power Advantage Tool Control Console
Getting to Know the Power Advantage Tool Control Console
Selecting Displays
Related Links
Zynq UltraScale+ RFSoC Power Advantage Tool 2020.1 ZCU111
Document History
Power Advantage Tool
Related Links
Zynq UltraScale＋ RFSoC Power Advantage Tool 2019.2 ZCU216
Zynq UltraScale＋RFSoC Power Advantage Tool 2019.2 ZCU216
1 Power Advantage Tool
1.1 Launching the Power Advantage Tool Control Console
1.2 Getting to Know the Power Advantage Tool Control Console
1.3 Domain Control
1.4 Selecting Displays
Related Links
Zynq UltraScale＋ RFSoC Power Advantage Tool 2019.2 ZCU208
Zynq UltraScale＋RFSoC Power Advantage Tool 2019.2 ZCU208
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ RFSoC Power Advantage Tool 2019.1 ZCU111
Zynq UltraScale＋RFSoC Power Advantage Tool 2019.1 ZCU111
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2019.1
Preliminary
1 Power Advantage Tool
1.1 Launching the Power Advantage Tool Control Console
1.2 Getting to Know the Power Advantage Tool Control Console
1.3 Domain Control
1.4 PL Control
1.5 Selecting Displays
1.6 Linux
1.7 GUI
1.8 Telnet
1.9 Ubuntu
Related Links
Zynq UltraScale＋ RFSoC Power Advantage Tool 2018.3 ZCU111
1 Power Advantage Tool
1.1 Launching the Power Advantage Tool Control Console
1.2 Getting to Know the Power Advantage Tool Control Console
1.3 Domain Control
1.4 Selecting Displays
Related Links
Zynq UltraScale＋ RFSoC Power Advantage Tool 2018.2 ZCU111
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2018.1 ZCU106
1 Power Advantage Tool
1.1 Launching the Power Advantage Tool Control Console
1.2 Getting to Know the Power Advantage Tool Control Console
1.3 Domain Control
1.4 PL Control
1.5 Selecting Displays
1.6 Linux
1.7 GUI
1.8 Telnet
1.9 Ubuntu
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2018.1
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2017.4
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2017.1 ZCU106
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2017.1
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2016.2
Document History
1.1 Launching the Power Advantage Tool Control Console
1.2 Getting to Know the Power Advantage Tool Control Console
1.3 Domain Control
1.4 Power Island Control
1.5 PL Control
1.6 Selecting Displays
1.7 Linux
1 Power Advantage Tool
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool 2016.3
1 Power Advantage Tool
Related Links
Zynq UltraScale+ MPSoC Power Advantage Tool 2020.2 Ultra96
Document History
Power Advantage Tool Parts
Power Advantage Tool Fabrication
Launching the Power Advantage Tool Control Console
Getting to Know the Power Advantage Tool Control Console
Selecting Displays
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 4 - Building and Running the SD Image
1.1 SD Image
1.1 Building the boot.bin
1.2 Using the SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 5 - Building and Running the PL Design From Sources
1 PL Design
1.1 Building the PL Design
1.2 Running the PL Design from the JTAG Debugger
1.3 Running the PL Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 6 - Building and Running the R5 Design From Sources
1 R5 Design
1.1 Building the R5 Design
1.2 Running the R5 Design from the JTAG Debugger
1.3 Running the R5 Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 7 - Building and Running the MSP430 Design from Sources
MSP430 Code
1.1 Building the MSP430 Design
1.2 Running the MSP430 Design from JTAG Debugger
1.3 Running the MSP430 Design from Flash
1.4 Deploying the MSP430 Design as a txt file
1.5 Flashing the MSP430 Design from a txt file with an MSP-FET JTAG cable
1.6 Flashing the MSP430 Design from a txt file without an MSP-FET JTAG cable
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 8 - Building and Running the Qt PC GUI Design from Sources
Qt PC Design
1.1 Build the Qt Design
1.2 Running the Qt Design from the Debugger
1.3 Deploying the Qt Design
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 9 - Building and Installing the Gimp Artwork from Sources
The Rich GUI experience is based on supporting layers of photo-realistic artwork. It is possible to modify the “skins” of the Power Advantage Tool at this level. This section will show you how to rebuild these GUI layers from source artwork.
Gimp Artwork
1.1 Rebuilding the Qt Artwork in Gimp
1.2 Installing the Qt Artwork
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool part 10 - Building and Running the Linux Design From Sources
1 Release-Specific Instructions
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool Linux 2016.3
1 Linux Design
1.1 Building the Linux Design
1.1 Preparing the Linux Kernel using the Petalinux 2016.3
1.2 Running the Linux Design from SD Image
1.2 Running the Linux Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool Linux 2017.1
1 Linux Design
1.1 Building the Linux Design
1.1 Preparing the Linux Kernel using the Petalinux 2017.1
1.2 Running the Linux Design from SD Image
1.2 Running the Linux Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool Linux 2018.1
1 Linux Design
1.1 Building the Linux Design
1.1 Preparing the Linux Kernel using PetaLinux 2018.1
1.2 Running the Linux Design from SD Image
1.2 Running the Linux Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Advantage Tool Linux 2019.1
1 Linux Design
1.1 Building the Linux Design
1.1 Preparing the Linux Kernel using PetaLinux 2019.1
1.2 Running the Linux Design from SD Image
1.2 Running the Linux Design from SD Image
Related Links
Zynq UltraScale＋ MPSoC Power Management - ZCU102 SW Design Examples
Before You Start
Prerequisites
Tips
Getting Started - Hello World
More Design Examples
Related Links
Zynq UltraScale＋ MPSoC Power Management - Firmware Examples
Node Assignments
DDR and PLL Nodes
Related Links
Zynq UltraScale＋ MPSoC Power Management - Software Tips
Disclaimer
Articles
ZU＋ PM Software Tips - UART Usage
UART Usage Considerations
Default PetaLinux Configuration
PMU Logging
Final Thoughts
Related Links
Zynq UltraScale＋ MPSoC Power Off Suspend
Introduction
Basic Operations
Design
Suspend and Power Off
Full Power to Power Off Suspend
LPD-only to Power Off Suspend
Power On and Resume
MSP430 Power Down Procedure
ZU+ / MSP430 Handshake
Configuration Changes
PMU Code Size Impacts
Porting to a Different Board
User Hooks
QSPI Flash Offset
Known Constraints
References
Zynq UltraScale＋ MPSoC Power Management - Linux Kernel
Prerequisites
Out-of-box PM Demo
Runtime PM
CPU PM
CPU Hotplug
CPU Idle
CPU Frequency
System PM
Suspend
Wake-up Source
UART
USB
Wake on LAN
GPIO
RTC
Global Storage Registers
Global General Storage Registers
Persistent Global General Storage Registers
Debugfs
Get API Version
Request Suspend
Self Suspend
Force Power Down
Abort Suspend
Request Wake-up
Set Wake-up Source
System Shutdown
Request Node
Release Node
Set Requirement
Set Max Latency
Get Node Status
Get Operating Characteristic
Reset Assert
Reset Get Status
MMIO Read
MMIO Write
Get Chip ID
Get pin control functions
Set pin control functions
Get configuration parameters for the pin
Set configuration parameters for the pin
Control device and configurations
Query Data
Enable Clock
Disable Clock
Get Clock State
Set Clock Divider
Get Clock Divider
Set Clock Rate
Get Clock Rate
Set Clock Parent
Get Clock Parent
CSU/PMU Register Access
Related Links

$ echo pm_clock_setdivider <clock id> <divider value> > (sysfs node)

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