GPIOs for PL Power Management Control

Zynq UltraScale plus MPSoC Power Management

Release Date

PL Power Management includes GPIO controls to clock managers so the PL clock domains can be frequency scaled or turned off. These are typically controlled externally to the PL by EMIO, AXI, or I2C. But they can also be controlled internally to the PL. Though the GPIOs are internal, the resources need to be reserved during the schematic design.