The Scharr function computes the gradients of input image in both x
and y direction by convolving the kernel with input image being
processed.
For Kernel size 3x3:
- GradientX:
- GradientY:
API Syntax
template<int BORDER_TYPE, int SRC_T,int DST_T, int ROWS, int COLS,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_X = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_Y = _XFCVDEPTH_DEFAULT>
void Scharr(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src_mat,xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_X> & _dst_matx,xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_Y> & _dst_maty)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| BORDER_TYPE | Border type supported is XF_BORDER_CONSTANT |
| SRC_T | Input pixel type. Only 8-bit, unsigned, 1 and 3 channels are supported (XF_8UC1 and XF_8UC3) |
| DST_T | Output pixel type. Only 8-bit unsigned, 16-bit signed,1 and 3 channels are supported (XF_8UC1, XF_16SC1,XF_8UC3 and XF_16SC3) |
| ROWS | Maximum height of input and output image |
| COLS | Maximum width of input and output image. Must be multiple of 8, for 8-pixel operation. |
| NPC | Number of pixels to be processed per cycle; possible options are XF_NPPC1 and XF_NPPC8 for 1 pixel and 8 pixel operations respectively. |
| XFCVDEPTH_IN | Depth of the input image. |
| XFCVDEPTH_OUT_X | Depth of the output image. |
| XFCVDEPTH_OUT_Y | Depth of the output image. |
| _src_mat | Input image |
| _dst_matx | X gradient output image. |
| _dst_maty | Y gradient output image. |
Resource Utilization
The following table summarizes the resource utilization of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.
| Name | Resource Utilization | |
|---|---|---|
| 1 pixel per clock operation | 8 pixel per clock operation | |
| 300 MHz | 150 MHz | |
| BRAM_18K | 3 | 6 |
| DSP48E | 0 | 0 |
| FF | 728 | 1434 |
| LUT | 812 | 2481 |
| CLB | 171 | 461 |
The following table summarizes the resource utilization of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a 4K 3 channel image.
| Name | Resource Utilization |
|---|---|
| 1 pixel per clock operation | |
| 300 MHz | |
| BRAM_18K | 18 |
| DSP48E | 0 |
| FF | 1911 |
| LUT | 1392 |
Performance Estimate
The following table summarizes the performance of the kernel in different configurations, as generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.
| Operating Mode | Operating Frequency (MHz) |
Latency (ms) |
|---|---|---|
| 1 pixel | 300 | 7.2 |
| 8 pixel | 150 | 1.7 |