The Reduce function reduces the matrix to a vector by treating rows/cols as set of 1-D vectors and performing specified operation on vectors until a single row/col is obtained.
Reduction operation could be one of the following:
- REDUCE_SUM : The output is the sum of all of the matrix’s rows/columns.
- REDUCE_AVG : The output is the mean vector of all of the matrix’s rows/columns.
- REDUCE_MAX : The output is the maximum (column/row-wise) of all of the matrix’s rows/columns.
- REDUCE_MIN : The output is the minimum (column/row-wise) of all of the matrix’s rows/columns.
API Syntax
template< int REDUCE_OP, int SRC_T , int DST_T, int ROWS, int COLS, int ONE_D_HEIGHT, int ONE_D_WIDTH,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>
void reduce(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src_mat, xf::cv::Mat<DST_T, ONE_D_HEIGHT, ONE_D_WIDTH, 1, XFCVDEPTH_OUT> & _dst_mat, unsigned char dim)
Parameter Descriptions
The following table describes the template and the function parameters.
| Parameter | Description |
|---|---|
| REDUCE_OP | The flag specifies the type of reduction operation to be applied. |
| SRC_T | Input pixel type. 8-bit, unsigned, 1 channel is supported (XF_8UC1). |
| DST_T | Output pixel type. 8-bit, unsigned, 1 channel is supported (XF_8UC1). |
| ROWS | Maximum height of input and output image |
| COLS | Maximum width of input and output image. In case of N-pixel parallelism, width should be multiple of N. |
| ONE_D_HEIGHT | Height of output 1-D vector or reduced matrix |
| ONE_D_WIDTH | Width of output 1-D vector or reduced matrix |
| NPC | Number of pixels to be processed per cycle; possible option is XF_NPPC1 (1 pixel per cycle). |
| XFCVDEPTH_IN | Depth of the input image. |
| XFCVDEPTH_OUT | Depth of the output image. |
| _src_mat | Input image |
| _dst_mat | 1-D vector |
| dim | Dimension index along which the matrix is reduced. 0 means that the matrix is reduced to a single row. 1 means that the matrix is reduced to a single column. |
Resource Utilization
The following table summarizes the resource utilization of the Reduce function Normal mode(1 pixel) as generated using Vivado HLS 2019.1 version tool for the Xczu9eg-ffvb1156-1-i-es1 FPGA.
| Name | Resource Utilization |
|---|---|
| 1 pixel per clock operation | |
| 300 MHz | |
| BRAM_18K | 2 |
| DSP48E | 0 |
| FF | 288 |
| LUT | 172 |
| CLB | 54 |
Performance Estimate
The following table summarizes a performance estimate of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for Xczu9eg-ffvb1156-1-i-es1 FPGA to process a grayscale HD (1080x1920) image.
| Operating Mode | Latency Estimate |
|---|---|
| Max Latency (ms) | |
| 1 pixel operation (300 MHz) | 6.9 |