The
integral
function computes an integral image of the input.
Each output pixel is the sum of all pixels above and to the left of
itself.API Syntax
template<int SRC_TYPE,int DST_TYPE, int ROWS, int COLS, int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>
void integral(xf::cv::Mat<SRC_TYPE, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src_mat, xf::cv::Mat<DST_TYPE, ROWS, COLS, NPC, XFCVDEPTH_OUT> & _dst_mat)
Parameter Descriptions
The following table describes the template and the function parameters.
Parameter | Description |
---|---|
SRC_TYPE | Input pixel type. Only 8-bit, unsigned, 1 channel is supported (XF_8UC1) |
DST_TYPE | Output pixel type. Only 32-bit,unsigned,1 channel is supported(XF_32UC1) |
ROWS | Maximum height of input and output image. |
COLS | Maximum width of input and output image |
NPC | Number of pixels to be processed per cycle; this function supports only XF_NPPC1 or 1 pixel per cycle operations. |
XFCVDEPTH_IN | Depth of the input image. |
XFCVDEPTH_OUT | Depth of the output image. |
_src_mat | Input image |
_dst_mat | Output image |
Resource Utilization
The following table summarizes the resource utilization of the kernel in different configurations, generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1 FPGA, to process a grayscale HD (1080x1920) image.
Name | Resource Utilization |
---|---|
1 pixel per clock operation | |
300 MHz | |
BRAM_18K | 4 |
DSP48E | 0 |
FF | 613 |
LUT | 378 |
CLB | 102 |
Performance Estimate
The following table summarizes the performance of the kernel in different configurations, as generated using Vivado HLS 2019.1 tool for the Xilinx Xczu9eg-ffvb1156-1-i-es1, to process a grayscale HD (1080x1920) image.
Operating Mode | Latency Estimate |
---|---|
Max Latency (ms) | |
1 pixel operation (300 MHz) | 7.2 |