BGR2NV21 - 2024.1 English

Vitis Libraries

Release Date
2024-05-30
Version
2024.1 English
template <int SRC_T, int Y_T, int UV_T, int ROWS, int COLS, int NPC=1,int NPC_UV=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_0 = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT_1 = _XFCVDEPTH_DEFAULT>void bgr2nv21(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src, xf::cv::Mat<Y_T, ROWS, COLS, NPC, XFCVDEPTH_OUT_0> & _y, xf::cv::Mat<UV_T, ROWS/2, COLS/2, NPC_UV, XFCVDEPTH_OUT_1> & _uv)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 465 Table Parameter Description
Parameter Description
SRC_T Input pixel type. Only 8-bit, unsigned, 3-channel is supported (XF_8UC3).
Y_T Output pixel type. Only 8-bit, unsigned, 1-channel is supported (XF_8UC1).
UV_T Output pixel type. Only 8-bit, unsigned, 2-channel is supported (XF_8UC2).
ROWS Maximum height of input and output image
COLS Maximum width of input and output image. Must be a multiple of NPC for N pixel mode.
NPC Number of Pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8.
NPC_UV Number of Pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2 and XF_NPPC4
XFCVDEPTH_IN Depth of input image
XFCVDEPTH_OUT_0 Depth of output image
XFCVDEPTH_OUT_1 Depth of output image
_src RGB input image of size(ROWS,COLS)
_y Output Y image of size (ROWS, COLS).
_uv Output UV image of size (ROWS/2, COLS/2).

Resource Utilization

The following table summarizes the resource utilization of RGB/BGR to NV12/NV21 function in Normal mode (1-Pixel), as generated in the Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Operating Mode Operating Frequency (MHz) Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 Pixel 300 0 9 413 279 66

Performance Estimate

The following table summarizes the performance of the kernel in single pixel configuration as generated using Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Table 466 Table Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9