UYVY2BGR: - 2024.1 English

Vitis Libraries

Release Date
2024-05-30
Version
2024.1 English
template<int SRC_T,int DST_T,int ROWS,int COLS,int NPC=1, int XFCVDEPTH_IN = _XFCVDEPTH_DEFAULT, int XFCVDEPTH_OUT = _XFCVDEPTH_DEFAULT>void uyvy2bgr(xf::cv::Mat<SRC_T, ROWS, COLS, NPC, XFCVDEPTH_IN> & _src,xf::cv::Mat<DST_T, ROWS, COLS, NPC, XFCVDEPTH_OUT> & _dst)

Parameter Descriptions

The following table describes the template and the function parameters.

Table 459 Table Parameter Description
Parameter Description
SRC_T Input pixel type. Only 16-bit, unsigned,1-channel is supported (XF_16UC1).
DST_T Output pixel type. Only 8-bit, unsigned, 3-channel is supported (XF_8UC3).
ROWS Maximum height of input and output image
COLS Maximum width of input and output image. Must be a multiple of NPC for N pixel mode.
NPC Number of Y pixels to be processed per cycle. Possible options are XF_NPPC1,XF_NPPC2,XF_NPPC4 and XF_NPPC8.
XFCVDEPTH_IN Depth of input image
XFCVDEPTH_OUT Depth of output image
_src Input image of size(ROWS, COLS)
_dst Output image of size (ROWS, COLS).

Resource Utilization

The following table summarizes the resource utilization of UYVY/YUYV to RGB/BGR function in Normal mode(1-Pixel), as generated in the Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Operating Mode Operating Frequency (MHz) Utilization Estimate
BRAM_18K DSP_48Es FF LUT CLB
1 Pixel 300 0 6 444 486 109

Performance Estimate

The following table summarizes the performance of the kernel in single pixel configuration as generated using Vivado HLS 2019.1 tool for the Xilinx xczu9eg-ffvb1156-2-i-es2 FPGA to process a HD (1080x1920) image.

Table 460 Table Performance Estimate Summary
Operating Mode Latency Estimate
Max Latency (ms)
1 pixel operation (300 MHz) 6.9